DP8572AN National Semiconductor, DP8572AN Datasheet - Page 15

• Manufacturer Part Number: DP8572AN
• Description: IC REAL TIME CLOCK W/RAM 24 DIP
• Manufacturer: National Semiconductor
• Type: Clock/Calendar/NVSRAMr

Specifications of DP8572AN

• Memory Size: 44B
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8572AN; DP8572

Functional Description
MAIN STATUS REGISTER
The Main Status Register is always located at address 0
regardless of the register block or the page selected
D0 This read only bit is a general interrupt status bit that is
taken directly from the interrupt pins The bit is a one when
an interrupt is pending on either the INTR pin or the MFO
pin (when configured as an interrupt) This is unlike D3
which can be set by an internal event but may not cause an
interrupt This bit is reset when the interrupt status bits in the
Main Status Register are cleared
D1 –D3 These three bits of the Main Status Register are the
main interrupt status bits Any bit may be a one when any of
the interrupts are pending Once an interrupt is asserted the
interrupt status bits are not reset when read Except for D1
to reset an interrupt a one is written back to the correspond-
ing bit that is being tested D1 is reset whenever the PFAIL
pin
reading the register in a polled mode D1 and D3 are set
regardless of whether these interrupts are masked or not by
bits D6 and D7 of Interrupt Control Registers 0 and 1
D4 –D5 General purpose RAM bits
D6 and D7 These bits are Read Write bits that control
which register block or RAM page is to be selected Bit D6
controls the register block to be accessed (see memory
map) The memory map of the clock is further divided into
two memory pages One page is the registers clock and
timers and the second page contains 31 bytes of general
purpose RAM The page selection is determined by bit D7
PERIODIC FLAG REGISTER
P will read this register to determine the cause These
e
logic 1 This prevents loss of interrupt status when
(Continued)
TL F 9980 – 12
TL F 9980 – 13
15
The Periodic Flag Register has the same bit for bit corre-
spondence as Interrupt Control Register 0 except for D6
and D7 For normal operation (i e not a single supply appli-
cation) this register must be written to on initial power up or
after an oscillator fail event D0 – D5 are read only bits D6
and D7 are read write
D0– D5 These bits are set by the real time rollover events
(Time Change
read and can be used as selective data change flags
D6 This bit performs a dual function When this bit is read a
one indicates that an oscillator failure has occurred and the
time information may have been lost Some of the ways an
oscillator failure might be caused are failure of the crystal
shorting OSC IN or OSC OUT to GND or V
crystal removal of battery when in the battery backed mode
(when a ‘‘0’’ is written to D6) lowering the voltage at the
V
backed mode Bit D6 is automatically set to 1 on initial pow-
er-up or an oscillator fail event The oscillator fail flag is
reset by writing a one to the clock start stop bit in the Real
Time Mode Register with the crystal oscillating
When D6 is written to it defines whether the TCP is being
used in battery backed (normal) or in a single supply mode
application When set to a one this bit configures the TCP
for single power supply applications This bit is automatically
set on initial power-up or an oscillator fail event When set
D6 disables the oscillator reference circuit The result is that
the oscillator is referenced to V
D6 the oscillator reference is enabled thus the oscillator is
referenced to V
standby applications
At initial power on if the DP8572A is going to be pro-
grammed for battery backed mode the V
connected to a potential in the range of 2 2V to V
0 4V
For single supply mode operation the V
connected to GND and the PFAIL pin connected to V
D7 Writing a one to this bit enables the test mode register
at location 1F (see Table III) This bit should be forced to
zero during initialization for normal operation If the test
mode has been entered clear the test mode register before
leaving test mode (See separate test mode application
note for further details )
TIME SAVE CONTROL REGISTER
D0– D4 General purpose RAM bits
BB
pin to a value less than 2 2V when in the battery
e
BB
1) The bits are reset when the register is
This allows operation in standard battery
CC
When a zero is written to
BB
BB
CC
pin should be
pin should be
removal of
TL F 9980 – 14
CC
CC
b