M41T81MX6 STMicroelectronics, M41T81MX6 Datasheet - Page 9

• Manufacturer Part Number: M41T81MX6
• Description: IC RTC SERIAL W/ALARM 28-SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/Alarmr

Specifications of M41T81MX6

• Memory Size: 20B
• Time Format: HH:MM:SS:hh (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2822-5

M41T81
2.2
Note:
Figure 4.
Figure 5.
READ mode
In this mode the master reads the M41T81 slave after setting the slave address (see
Figure 7 on page
bit, the word address 'An' is written to the on-chip address pointer. Next the START condition
and slave address are repeated followed by the READ mode control bit (R/W=1). At this
point the master transmitter becomes the master receiver. The data byte which was
addressed will be transmitted and the master receiver will send an acknowledge bit to the
slave transmitter. The address pointer is only incremented on reception of an acknowledge
clock. The M41T81 slave transmitter will now place the data byte at address An+1 on the
bus, the master receiver reads and acknowledges the new byte and the address pointer is
incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume due to a stop condition or when the
pointer increments to any non-clock address (08h-13h).
This is true both in READ mode and WRITE mode.
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
CLOCK
DATA
Serial bus data transfer sequence
CONDITION
Acknowledgement sequence
START
10). Following the WRITE mode control bit (R/W=0) and the acknowledge
START
MSB
Doc ID 7529 Rev 10
1
DATA VALID
DATA LINE
STABLE
DATA ALLOWED
CHANGE OF
2
LSB
8
ACKNOWLEDGEMENT
CLOCK PULSE FOR
CONDITION
STOP
Operation
9
AI00587
AI00601
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