ISL12024IRTCZ-T Intersil, ISL12024IRTCZ-T Datasheet - Page 15

• Manufacturer Part Number: ISL12024IRTCZ-T
• Description: IC RTC/CALENDER 64BIT 8-TDFN
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12024IRTCZ-T

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

.
Serial Communication
The device supports the I
Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (see Figure 12).
Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met (see Figure 13).
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby Power Mode after a read sequence. A stop
V
BAT
FIGURE 11. BATTERY SWITCHOVER IN LEGACY MODE
OFF
V
DD
SDA
SCL
SDA
SCL
2
C protocol.
15
VOLTAGE
FIGURE 12. VALID DATA CHANGES ON THE SDA BUS
FIGURE 13. VALID START AND STOP CONDITIONS
DATA STABLE
ON
START
ISL12024IRTCZ
In
DATA CHANGE
condition can only be issued after the transmitting device
has released the bus (see Figure 13).
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting 8 bits.
During the ninth clock cycle, the receiver will pull the SDA
line LOW to acknowledge that it received the 8 bits of data
(see Figure 14).
The device will respond with an acknowledge after
recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave Address
Byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
8-bit word. The device will not acknowledge if the slave
address byte is incorrect.
In the read mode, the device will transmit 8-bits of data,
release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will continue
to transmit data. The device will terminate further data
transmissions if an acknowledge is not detected. The master
must then issue a stop condition to return the device to
Standby Power Mode and place the device into a known
state.
DATA STABLE
STOP
August 8, 2008
FN6749.0