ISL12024IRTCZ-T Intersil, ISL12024IRTCZ-T Datasheet

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... Data Sheet Real-Time Clock/Calendar with Embedded Unique ID The ISL12024IRTCZ device is a micro-power real-time clock with embedded 64-bit unique ID, timing and crystal compensation, clock/calender, power-fail indicator, two periodic or polled alarms, intelligent battery backup switching, and integrated 512x8-bit EEPROM configured in 16 Bytes per page. ...

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... The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). 7 FVBAT This input provides a backup supply voltage to the device supply fails. This pin should be tied to ground if not used VDD Power Supply. 2 ISL12024IRTCZ OSC COMPENSATION TIMER FREQUENCY 1Hz OSCILLATOR CALENDAR DIVIDER LOGIC STATUS CONTROL/ ...

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... IRQ/F OUT V Output Low Voltage OL I Output Leakage Current LO 3 ISL12024IRTCZ Thermal Information Thermal Resistance (Typical, Notes 1, 2) θ OUT Pins TDFN Package . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = +2.7V to +5.5V -40°C to +85°C, Typical values are @ T ...

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... Input Data Set-up Time SU:DAT t Input Data Hold Time HD:DAT t STOP Condition Set-up Time SU:STO t STOP Condition Hold Time for HD:STO Read, or Volatile Only Write t Output Data Hold Time DH 4 ISL12024IRTCZ TEST CONDITIONS Temperature ≤ +75°C TEST CONDITIONS (Note 12 4mA 5. 5.5V IN ...

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... HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) Write Cycle Timing SCL SDA 8TH BIT OF LAST BYTE 5 ISL12024IRTCZ TEST CONDITIONS From 30 From 70 Maximum is determined by t and For Cb = 400pF, max is about 2kΩ~2.5kΩ. For Cb = 40pF, max is about 15kΩ~20kΩ ...

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... V (V) DD FIGURE DD3 6 ISL12024IRTCZ Temperature is +25°C unless otherwise specified. 0.9 0.8 0.7 0.6 0.5 0.4 0.3 BAT 0.2 0.1 0.0 4.3 4.8 5.3 SBIB = 0 1.4 1.2 1 ...

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... The X1 and X2 pins are the input and output, respectively, of OUT an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL12024IRTCZ to supply a timebase for the real-time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from -40°C to +85°C. This oscillator compensation network can be used to ...

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... CCR. Prior to writing to the CCR (except the status register), 8 ISL12024IRTCZ however, the WEL and RWEL bits must be set using a three step process (see section See “Writing to the Clock/Control Registers” on page 12.) The CCR is divided into 6 sections. These are: 1. Alarm 0 (8 bytes ...

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... This bit set to “1” indicates that the device is operating from V , not read-only bit and is set/reset by BAT DD hardware (ISL12024IRTCZ internally). Once the device begins operating from V , the device sets this bit to “0”. DD AL1, AL0: Alarm Bits - Volatile These bits announce if either alarm 0 or alarm 1 match the real-time clock. If there is a match, the respective bit is set to ‘ ...

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... MOA0 EMO0 0003 DTA0 EDT0 0002 HRA0 EHR0 0001 MNA0 EMN0 0000 SCA0 ESC0 NOTE: Shaded cells indicate that NO other value written to that bit. *Indicates set at the factory, read only: 10 ISL12024IRTCZ TABLE 2. CLOCK/CONTROL MEMORY MAP BIT AL1 AL0 Y2K21 Y2K20 Y2K13 0 ...

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... FO0 bits are set disabled). OUT 11 ISL12024IRTCZ The IM bit enables the pulsed interrupt mode. To enter this mode, the AL0E or AL1E bits are set to “1”, and the IM bit to “1”. The IRQ/F alarm occurs. This means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time ...

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... ISL12024IRTCZ TABLE 5. DIGITAL TRIMMING REGISTERS (Continued) DTR2 1 PWR Register: SBIB, BSW SBIB: Serial Bus Interface (Enable) The serial bus can be disabled in Battery Backup Mode by setting this bit to “1”. This will minimize power drain on the battery. The Serial Interface can be enabled in Battery Backup Mode by setting this bit to “ ...

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... Specifically, byte writes to individual registers are good for all 13 ISL12024IRTCZ but registers 0006h and 0000Eh, which are the DWA0 and DWA1 registers, respectively. Those registers will require a special page write for nonvolatile storage. The recommended page write sequences are as follows: 1 ...

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... V BATHYS - Condition 2: V < TRIP ≈ 2.2V where V TRIP • Battery Backup Mode ( Normal Mode (V BAT The ISL12024IRTCZ device will switch from the V V mode when one of the following conditions occurs Condition 1: V > BAT BATHYS ≈ 50mV where V BATHYS ...

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... HIGH. The stop condition is also used to place the device into the Standby Power Mode after a read sequence. A stop SCL SDA SCL SDA 15 ISL12024IRTCZ condition can only be issued after the transmitting device has released the bus (see Figure 13). ON Acknowledge In Acknowledge is a software convention used to indicate successful data transfer ...

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... The last bit of the Slave Address Byte defines the operation to be performed. When this R/W bit is a one, then a read operation is selected. A zero selects a write operation (see Figure 15.) After loading the entire Slave Address Byte from the SDA bus, the ISL12024IRTCZ compares the device identifier and DEVICE IDENTIFIER ARRAY 1 0 ...

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... Clock/Control Registers” on page 12). Upon receipt of each address byte, the ISL12024IRTCZ responds with an acknowledge. After receiving both address bytes the ISL12024IRTCZ awaits the 8 bits of data. After receiving the 8 data bits, the ISL12024IRTCZ again responds with an acknowledge. The master then terminates the transfer by generating a stop condition ...

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... Upon receipt of the Slave Address Byte with the R/W bit set to one, the ISL12024IRTCZ issues an acknowledge, then transmits 8 data bits. The master terminates the read operation by not responding with an acknowledge during the ninth clock and issuing a stop condition ...

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... In a similar operation called “Set Current Address,” the device sets the address if a stop is issued instead of the second start shown in Figure 21. The ISL12024IRTCZ then goes into Standby Power Mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter ...

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... This control is handled by the Analog Trimming Register, or ATR, which TABLE 6. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTCs PARAMETER Frequency Frequency Tolerance Turnover-temperature Operating Temperature Range Parallel Load Capacitance Equivalent Series Resistance 20 ISL12024IRTCZ DATA DATA K (2) (1) FIGURE 22 ...

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... PCB layers in the vicinity of the RTC device. A small decoupling capacitor at the V pin of the chip is mandatory, DD with a solid connection to ground. The ISL12024IRTCZ product has a special consideration. The IRQ/F pin on the 8 Ld TDFN package is located OUT next to the X2 pin. When this pin is used as a frequency output (IRQ/F ) and is set to 32 ...

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... Alarm0 set with single interrupt (IM = “0”) A single alarm will occur on January 1 at 11:30am. A. Set Alarm0 registers as follows: BIT ALARM0 REGISTER HEX SCA0 MNA0 ISL12024IRTCZ ALARM0 REGISTER HRA0 DTA0 MOA0 to charge the DWA0 pin. Try to BAT desirable. µA B. Also, the AL0E bit must be set as follows: ...

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... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 23 ISL12024IRTCZ also powered by the battery, then the ISL12024IRTCZ can communicate in Battery Backup Mode. • Mode this mode selection, bits indicate Legacy Mode switchover combined with I Backup Mode ...

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... Rev 0 6/08 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 2. 1.95) (1.64) ( 2.80 ) (6x 0.65) TYPICAL RECOMMENDED LAND PATTERN 24 ISL12024IRTCZ 2X 1.950 0.400 ± 0.10 Max 0. 0.60 0.30) NOTES: 1. Dimensions are in millimeters. Dimensions Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4 ...