ISL12027IB27AZ Intersil, ISL12027IB27AZ Datasheet - Page 5
![no-image](/images/manufacturer_photos/0/3/341/intersil_sml.jpg)
ISL12027IB27AZ
Manufacturer Part Number
ISL12027IB27AZ
Description
IC RTC/CALENDAR EEPROM 8-SOIC
Manufacturer
Intersil
Type
Clock/Calendar/Supervisor/EEPROMr
Specifications of ISL12027IB27AZ
Memory Size
4K (512 x 8)
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Clock Format
HH
Clock Ic Type
RTC
Interface Type
I2C, Serial
Memory Configuration
512 X 8
Supply Voltage Range
2.7V To 5.5V
Digital Ic Case Style
SOIC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISL12027IB27AZ
Manufacturer:
Intersil
Quantity:
669
Part Number:
ISL12027IB27AZ
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
ISL12027IB27AZ-T
Manufacturer:
SST
Quantity:
1 200
Watchdog Timer/Low Voltage Reset Parameters
Serial Interface (I
EEPROM SPECIFICATIONS
TIMING CHARACTERISTICS
Hysteresis SDA and SCL Input Buffer
SYMBOL
SYMBOL
V
V
t
t
PURST
t
RVALID
t
f
t
RESET
V
HIGH
t
t
LOW
t
V
WDO
V
I
SCL
t
BUF
RPD
RST
RSP
t
I
LO
AA
IN
OL
LI
IH
IL
SDA, and SCL Input Buffer LOW
Voltage
SDA, and SCL Input Buffer HIGH
Voltage
Hysteresis
SDA Output Buffer LOW Voltage
Input Leakage Current on SCL
I/O Leakage Current on SDA
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
V
Power-up Reset Time-Out Delay
Minimum V
Output
ISL12027-4.5A Reset Voltage Level
ISL12027 Reset Voltage Level
ISL12027-3 Reset Voltage Level
ISL12027-2.7A Reset Voltage Level
ISL12027-2.7 Reset Voltage Level
Watchdog Timer Period
Watchdog Timer Reset Time-Out
Delay
I
EEPROM Endurance
EEPROM Retention
2
DD
C Interface Minimum Restart Time
Detect to RESET LOW
2
PARAMETER
C) Specifications
PARAMETER
DD
for Valid RESET
5
SBIB = 1 (Under V
SBIB = 1 (Under V
SBIB = 1 (Under V
I
V
V
Any pulse narrower than the max spec
is suppressed.
SCL falling edge crossing 30% of V
until SDA exits the 30% to 70% of V
window.
SDA crossing 70% of V
STOP condition, to SDA crossing 70%
of V
condition.
Measured at the 30% of V
Measured at the 70% of V
32.768kHz crystal between X1
Temperature ≤75°C
OL
and X2
32.768kHz crystal between X1
and X2
IN
IN
= 4mA
= 5.5V
= 5.5V
DD
during the following START
CONDITIONS
CONDITIONS
ISL12027
DD
DD
DD
mode)
mode)
mode)
DD
DD
DD
during a
crossing.
crossing.
DD
DD
>2,000,000
,
0.05 x V
MIN
4.59
4.33
3.04
2.87
2.58
1.70
100
725
225
225
0.7 x V
1.0
1.2
50
1300
1300
MIN
-0.3
600
0
DD
DD
(Note 5)
TYP
4.64
4.38
3.09
2.92
2.63
1.75
500
250
750
250
250
TYP
0.1
0.1
0.3 x V
V
1.801
MAX
4.69
4.43
3.14
2.97
2.68
DD
400
775
275
275
MAX
400
900
0.4
10
10
50
+ 0.3
DD
UNITS
UNITS
Cycles
Years
kHz
ms
ms
ms
ms
µA
µA
ns
ns
ns
µs
ns
ns
ns
V
V
V
V
V
V
V
V
V
V
s
October 18, 2006
NOTES
NOTES
FN8232.4
9