M48T37V-10MH1E STMicroelectronics, M48T37V-10MH1E Datasheet - Page 15

• Manufacturer Part Number: M48T37V-10MH1E
• Description: IC TIMEKPR NVRAM 256KBIT3V 44SOH
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T37V-10MH1E

• Memory Size: 256K (32K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-SOH
• Function: Clock/Calendar/NV Timekeeping RAM/Watchdog Timer/Battery Backup/Alarm
• Rtc Memory Size: 32768 Byte
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Parallel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2852-5; M48T37V-10MH1

M48T37Y, M48T37V
3.5
Figure 8.
Calibrating the clock
The M48T37Y/V is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not to exceed ±35 ppm (parts per million) oscillator
frequency error at 25 °C, which equates to about ±1.53 minutes per month. With the
calibration bits properly set, the accuracy of each M48T37Y/V improves to better than
+1/–2 ppm at 25 °C.
The oscillation rate of any crystal changes with temperature (see
Most clock chips compensate for crystal frequency and temperature shift error with
cumbersome trim capacitors. The M48T37Y/V design, however, employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five-bit calibration byte found in the control register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The calibration byte occupies the five lower order bits (D4-D0) in the control register 7FF8h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the
sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125, 829, 120 (64 minutes x 60 seconds/minute x 32,768 cycles/second)
actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in
the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz,
each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds
per month which corresponds to a total range of +5.5 or –2.75 minutes per month.
V CC
V PFD (max)
V PFD (min)
V SO
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT
Backup mode alarm waveforms
HIGH-Z
Doc ID 7019 Rev 9
Figure 11 on page
19. The number of times pulses
Figure 10 on page
tREC
Clock operations
HIGH-Z
19).
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