M41ST87WSS6F STMicroelectronics, M41ST87WSS6F Datasheet - Page 41

• Manufacturer Part Number: M41ST87WSS6F
• Description: IC SUPERVISOR RTC/NVRAM 20-SSOP
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/Supervisorr

Specifications of M41ST87WSS6F

• Memory Size: 160B
• Time Format: HH:MM:SS:hh (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Function: Clock, Timestamp, Timekeeper, Watchdog, Alarm, Calendar, Timer, Timer Interrupt
• Rtc Memory Size: 1280 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial
• Supply Current: 500 nA
• Clock Format: Ss
• Clock Ic Type: RTC
• Interface Type: I2C
• Memory Configuration: 128 X 8
• Supply Voltage Range: 2.7V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10616-2

M41ST87Y, M41ST87W
3.17
Table 13.
1. When TEB
2. UC = unchanged.
3. ⇑ = V
4. WDS, BMB0-BMB4, RB0, RB1.
5. 32 kHz output valid only on V
Note:
Initial power-up
Subsequent power-up (with
battery backup)
Initial power-up
Subsequent power-up (with
battery backup)
Initial power-up
Subsequent power-up (with
battery backup)
Initial power-up
Subsequent power-up (with
battery backup)
CC
Condition
Condition
Condition
Condition
rising; ⇓ = V
X
Initial power-on defaults
Default values
All other control bits are undetermined.
is set to '1,' the HT bit will not be set on power-down (tamper time-stamp will have precedence).
(2)(3)
(2)(3)
(2)
(2)
CC
falling.
CC
TCHI/TCLO1
.
and 2
32kE
ABE
UC
1
UC
UC
TR
0 ⇑
0
0
0
(5)
SQWE
CLR1
and 2
THS
UC
0 ⇑
UC
UC
ST
Doc ID 9497 Rev 9
0
0
0
0
TEB1 and 2
TIE1 and 2
SQWOD
UC
UC
UC
0 ⇑
OF
1
1
0
0
TCM1 and 2
CLRPW0
PFOD
OFIE
0 ⇑
UC
UC
UC
0
1
0
0
HT
TPM1 and 2
1 ⇓
1
CLRPW1
(1)
Watchdog register
UC
UC
0
0
Out
UC
1
Clock operation
0 ⇓
0
TDS1 and 2
0 ⇓
CLR1
CLR2
FT
0
and
UC
UC
0
0
(4)
EXT
EXT
41/54
AFE
0 ⇑
0