M41T00SM6F STMicroelectronics, M41T00SM6F Datasheet - Page 9
![IC RTC SERIAL ACCESS 8-SOIC](/photos/1/38/13851/497-8-soic_sml.jpg)
M41T00SM6F
Manufacturer Part Number
M41T00SM6F
Description
IC RTC SERIAL ACCESS 8-SOIC
Manufacturer
STMicroelectronics
Type
Clock/Calendar/NVSRAMr
Datasheet
1.M41T00SM6F.pdf
(26 pages)
Specifications of M41T00SM6F
Memory Size
8B
Time Format
HH:MM:SS (24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-6458-2
M41T00SM6F
M41T00SM6F
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M41T00SM6F
Manufacturer:
ST
Quantity:
20 000
Figure 5.
2.2
Note:
Figure 6.
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
Acknowledgement sequence
READ mode
In this mode the master reads the M41T00S slave after setting the slave address (see
Figure 7 on page
bit, the word address 'An' is written to the on-chip address pointer. Next the START condition
and slave address are repeated followed by the READ mode control bit (R/W=1). At this
point the master transmitter becomes the master receiver. The data byte which was
addressed will be transmitted and the master receiver will send an acknowledge bit to the
slave transmitter. The address pointer is only incremented on reception of an acknowledge
clock. The M41T00S slave transmitter will now place the data byte at address An+1 on the
bus, the master receiver reads and acknowledges the new byte and the address pointer is
incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 06h). The update will resume due to a stop condition or when the
pointer increments to any non-clock address (07h).
This is true both in READ mode and WRITE mode.
An alternate READ mode may also be implemented whereby the master reads the
M41T00S slave without first writing to the (volatile) address pointer. The first address that is
read is the last one stored in the pointer (see
Slave address location
START
START
10). Following the WRITE mode control bit (R/W=0) and the acknowledge
MSB
1
1
1
SLAVE ADDRESS
0
2
1
0
Figure 8 on page
0
0
R/W
A
LSB
AI00602
8
10).
ACKNOWLEDGEMENT
CLOCK PULSE FOR
9
AI00601
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