PCF2123BS/1,518 NXP Semiconductors, PCF2123BS/1,518 Datasheet - Page 24

• Manufacturer Part Number: PCF2123BS/1,518
• Description: IC RTC/CALENDAR SPI BUS 16HVQFN
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCF2123BS/1,518

• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.1 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935286382518

NXP Semiconductors
PCF2123
Product data sheet
8.6.5 Timer flags
therefore changing it without setting bit TE = 0 may result in a corrupted value loaded into
the countdown counter which results in an undetermined countdown period for the first
period. The countdown value n will, however, be correctly stored and correctly loaded on
subsequent timer periods.
When the countdown timer flag is set, an interrupt signal on INT will be generated
provided that this mode is enabled. See
be controlled.
When starting the timer for the first time, the first period will have an uncertainty which is a
result of the enable instruction being generated from the interface clock which is
asynchronous from the timer source clock. Subsequent timer periods will have no such
delay. The amount of delay for the first timer period will depend on the chosen source
clock, see
Table 29.
At the end of every countdown, the timer sets the countdown timer flag (bit TF). Bit TF
may only be cleared by software. The asserted bit TF can be used to generate an
interrupt (INT). The interrupt may be generated as a pulsed signal every countdown
period or as a permanently active signal which follows the condition of bit TF. Bit TI_TP is
used to control this mode selection and the interrupt output may be disabled with bit TIE,
see
When reading the timer, the current countdown value is returned and not the initial
value n. Since it is not possible to freeze the countdown timer counter during read back, it
is recommended to read the register twice and check for consistent results.
Timer source clock frequency selection of 1 Hz and
Offset_register. The duration of a program period will vary according to when the offset is
initiated. For example, if a 100 s timer is set using the 1 Hz clock as source, then some
100 s periods will contain correction pulses and therefor be longer or shorter depending
on the setting of the Offset_register. See
Offset_register.
When a minute or second interrupt occurs, bit MSF is set logic 1. Similarly, at the end of a
timer countdown or alarm event, bit TF or AF are set logic 1. These bits maintain their
value until overwritten by software. If both countdown timer and minute or second
interrupts are required in the application, the source of the interrupt can be determined by
reading these bits. To prevent one flag being overwritten while clearing another a logical
AND is performed during a write access. A flag is cleared by writing logic 0 whilst a flag is
not cleared by writing logic 1. Writing logic 1 will result in the flag value remaining
unchanged.
Timer source clock
4.096 kHz
64 Hz
1 Hz
1

60
Hz
Table
7.
Table
First period delay for timer counter value n
All information provided in this document is subject to legal disclaimers.
29.
Rev. 4 — 22 December 2010
Minimum timer period
n
n
(n 1) +
(n  1) +
1
1


64
64
Section 8.7.2
Section 8.9
Hz
Hz
1

to understand the operation of the
60
for details on how the interrupt can
Hz will be affected by the
SPI Real time clock/calendar
Maximum timer period
n + 1
n + 1
n +
n +
1
1


64
64
Hz
Hz
PCF2123
© NXP B.V. 2010. All rights reserved.
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