M41T0M6E STMicroelectronics, M41T0M6E Datasheet - Page 7
![IC RTC SERIAL 2V-5.5V 8SOIC](/photos/1/38/13851/497-8-soic_sml.jpg)
M41T0M6E
Manufacturer Part Number
M41T0M6E
Description
IC RTC SERIAL 2V-5.5V 8SOIC
Manufacturer
STMicroelectronics
Type
Clock/Calendar/NVSRAMr
Specifications of M41T0M6E
Memory Size
8B
Time Format
HH:MM:SS (24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Function
Clock/Calendar
Rtc Memory Size
8 Byte
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Rtc Bus Interface
Serial (2-Wire, I2C)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2812-5
M41T0M6
M41T0M6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M41T0M6E
Manufacturer:
ST
Quantity:
20 000
2
2.1
2.1.1
2.1.2
2.1.3
Operation
The M41T0 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 8 bytes
contained in the device can then be accessed sequentially in the following order:
1.
2.
3.
4.
5.
6.
7.
8.
2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bidirectional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
●
Accordingly, the following bus conditions have been defined:
Bus not busy
Both data and clock lines remain high.
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
Seconds register
Minutes register
Century/hours register
Day register
Date register
Month register
Years register
Control register
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is High.
Changes in the data line while the clock line is High will be interpreted as control
signals.
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