M41T66Q6F STMicroelectronics, M41T66Q6F Datasheet - Page 10
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M41T66Q6F
Manufacturer Part Number
M41T66Q6F
Description
IC RTC SERIAL W/ALARM 16-QFN
Manufacturer
STMicroelectronics
Type
Clock/Calendar/Alarmr
Datasheet
1.M41T66Q6F.pdf
(33 pages)
Specifications of M41T66Q6F
Memory Size
16B
Time Format
HH:MM:SS:hh (24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.5 V ~ 4.4 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8377-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M41T66Q6F
Manufacturer:
Maxim
Quantity:
178
Part Number:
M41T66Q6F
Manufacturer:
ST
Quantity:
20 000
Operation
2.2
Note:
10/33
Figure 6.
READ mode
In this mode the master reads the M41T66 slave after setting the slave address (see
Figure 8 on page
bit, the word address 'An' is written to the on-chip address pointer. Next the START condition
and slave address are repeated followed by the READ mode control bit (R/W=1). At this
point the master transmitter becomes the master receiver. The data byte which was
addressed will be transmitted and the master receiver will send an acknowledge bit to the
slave transmitter. The address pointer is only incremented on reception of an acknowledge
clock. The M41T66 slave transmitter will now place the data byte at address An+1 on the
bus, the master receiver reads and acknowledges the new byte and the address pointer is
incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume due to a stop condition or when the
pointer increments to any non-clock address (08h-0Fh).
This is true both in READ mode and WRITE mode.
An alternate READ mode may also be implemented whereby the master reads the M41T66
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see
Acknowledgement sequence
11). Following the WRITE mode control bit (R/W=0) and the acknowledge
Figure 9 on page
11).
M41T66