CY2XF23FLXCT Cypress Semiconductor Corp, CY2XF23FLXCT Datasheet - Page 7

• Manufacturer Part Number: CY2XF23FLXCT
• Description: IC XTAL OSC LVDS I2C 6CLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY2XF23FLXCT

• Pll: Yes
• Input: Crystal
• Output: LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/Yes
• Frequency - Max: 690MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 6-CLCC
• Frequency: *
• Count: *
• Operating Supply Voltage (typ): 2.5/3.3
• Output Level: LVDS
• Symmetry Max: 60%
• Operating Temp Range: 0C to 70C
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Absolute Maximum Conditions
Operating Conditions
DC Electrical Characteristics
Document Number: 001-53145 Rev. *D
V
V
T
T
ESD
Θ
V
T
T
I
V
ΔV
V
Notes
Parameter
Parameter
Parameter
DD
2. The voltage on any input or I/O pin cannot exceed the power pin during power up.
3. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
4. I
A
DD
IN
S
J
DD
PU
OD
OS
JA
OD
[2]
[4]
[3]
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
DD
HBM
SDA
includes ~4 mA of current that is dissipated externally in the output termination resistors.
SCLK
START
3.3-V supply voltage range
2.5-V supply voltage range
Power-up time for V
monotonic)
Ambient temperature (commercial)
Ambient temperature (industrial)
Operating supply current
LVDS differential output voltage
Change in V
complementary output states
LVDS offset output voltage
Supply voltage
Input voltage, DC
Temperature, storage
Temperature, junction
Electrostatic discharge (ESD) protection
human body model (HBM)
Thermal resistance, junction to ambient
DA6
Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)
Description
OD
DA5 DA0
Description
between
+
+
DD
to reach minimum specified voltage (power ramp is
R/W
ACK
Description
PRELIMINARY
V
terminated
V
terminated
V
as terminated in
V
as terminated in
V
as terminated in
DD
DD
DD
DD
DD
RA7
= 3.465 V, CLK = 150 MHz, output
= 2.625 V, CLK = 150 MHz, output
= 3.3 V or 2.5 V, defined in
= 3.3 V or 2.5 V, defined in
= 3.3 V or 2.5 V, defined in
Relative to V
Non Operating
JEDEC Std 22-A114-B
0 m/s airflow
RA6 RA1
+
+
Condition
Figure 13
Figure 13
Figure 13
Condition
SS
RA0
ACK
Figure 8
Figure 8
Figure 9
D7
D6
3.135
2.375
1.125
0.05
Min
Min
247
–40
2000
–0.5
–0.5
Min
–55
–40
0
–
–
–
+
+
D1
Typ
64
Typ
3.3
2.5
–
–
–
–
–
D0
–
–
–
V
DD
Max
135
135
4.4
–
ACK
1.375
+0.5
3.465
2.625
Max
120
115
454
Max
500
50
70
85
CY2XF23
Page 7 of 14
°C/W
Unit
Unit
Unit
STOP
mA
mA
mV
mV
°C
°C
ms
°C
°C
V
V
V
V
V
V
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