SI4133GX2-BM Silicon Laboratories Inc, SI4133GX2-BM Datasheet - Page 18

• Manufacturer Part Number: SI4133GX2-BM
• Description: SYNTH DUAL GSM RF(RF1/RF2/IF)
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4133GX2-BM

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Si4133G-X2
Reference Frequency Amplifier
The Si4133G-X2 provides a reference frequency
amplifier. If the driving signal has CMOS levels it can be
connected directly to the XIN pin. Otherwise, the
reference frequency signal should be ac coupled to the
XIN pin through a 560 pF capacitor.
Powerdown Modes
Table 8 summarizes the powerdown functionality. The
Si4133G-X2 can be powered down by taking the PWDN
pin low or by setting bits in the Powerdown register
(Register 2). When the PWDN pin is low, the Si4133G-
X2 is powered down regardless of the Powerdown
register settings. When the PWDN pin is high, power
management is under control of the Powerdown register
bits.
18
Figure 17. IFOUT 50 Ω Matching Network
IFOUT
PWDN Pin
PWDN = 0
PWDN = 1
18 nH
AUTOPDB
560 pF
0
0
0
0
1
x
Table 8. Powerdown Configuration
50 Ω
PDIB
x
0
0
1
1
x
Rev. 1.2
The reference frequency amplifier, IF, and RF sections
of the Si4133G-X2 circuitry can be individually powered
down by setting the Powerdown register bits PDIB and
PDRB low, respectively. The reference frequency
amplifier is also powered up if the PDRB and PDIB bits
are high. Also, setting the AUTOPDB bit to 1 in the Main
Configuration register (Register 0) is equivalent to
setting both bits in the Powerdown register to 1. The
serial interface remains available and can be written in
all powerdown modes.
Auxiliary Output (AUXOUT)
The signal appearing on AUXOUT is selected by setting
the AUXSEL bits in the Main Configuration register
(Register 0).
The LDETB signal can be selected by setting the
AUXSEL bits to 11. As discussed previously, this signal
can be used to indicate that the IF or RF PLL is about to
lose lock because of excessive ambient temperature
drift and should be re-tuned. The LDETB signal
indicates a logical OR result if both IF and RF are
simultaneously generating a signal.
PDRB
x
0
1
0
1
x
IF Circuitry
OFF
OFF
OFF
ON
ON
ON
RF Circuitry
OFF
OFF
OFF
ON
ON
ON