SI4133GX2-BM Silicon Laboratories Inc, SI4133GX2-BM Datasheet - Page 17

• Manufacturer Part Number: SI4133GX2-BM
• Description: SYNTH DUAL GSM RF(RF1/RF2/IF)
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4133GX2-BM

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The LDETB signal is low after self-tuning has completed
but rises when either the IF or RF PLL nears the limit of
its compensation range (LDETB is also high when either
PLL is executing the self-tuning algorithm). The output
frequency is still locked when LDETB goes high, but the
PLL eventually loses lock if the temperature continues
to drift in the same direction. Therefore, if LDETB goes
high both the IF and RF PLLs should promptly be re-
tuned by initiating the self-tuning algorithm.
Output Frequencies
The IF and RF output frequencies are set by
programming the N-Divider registers. Each RF PLL has
its
independently. All three PLL R-dividers are fixed at
R=65 to yield a 200 kHz phase detector update rate
from a 13 MHz reference frequency. Programming the
N-Divider register for either RF1 or RF2 automatically
selects the associated output.
The reference frequency on the XIN pin is divided by R
and this signal is input to the PLL’s phase detector. The
other input to the phase detector is the PLL’s VCO
output frequency divided by N. The PLL acts to make
these frequencies equal. That is, after an initial transient
The integer N is set by programming the RF1 N-Divider
register (Register 3), the RF2 N-Divider register
(Register 4), and the IF N-Divider register (Register 5).
Each N-divider is implemented as a conventional high
speed divider. That is, it consists of a dual-modulus
prescaler, a swallow counter, and a lower speed
synchronous counter. However, the calculation of these
values is done automatically. Only the appropriate N
value must be programmed
PLL Loop Dynamics
The transient response for each PLL is optimized for a
GSM application. VCO gain, phase detector gain, and
loop filter characteristics are not programmable.
The settling time for each PLL is directly proportional to
its phase detector update period T φ (T φ equals 1/f φ ). For
a GSM application with a 13 MHz reference frequency,
own
N
For XIN = 13 MHz this simplifies to
register
F
F
OUT
OUT
F
------------- -
OUT
N
=
or
=
and
N 200 kHz
=
----- -
65
N
×
F
-------------
×
65
REF
F
can
REF
be
programmed
Rev. 1.2
the RF and IF PLLs T φ = 5 µ S. During the first 6.5
update periods, the Si4133G-X2 executes the self-
tuning algorithm. Thereafter the PLL controls the output
frequency. Because of the unique architecture of the
Si4133G-X2 PLLs, the time required to settle the output
frequency to 0.1 ppm error is approximately 21 update
periods. Thus, the total time after powerup or a change
in
frequency is well settled (including time for self-tuning)
is around 28 update periods or 140 µ S.
RF and IF Outputs
The RFOUT and IFOUT pins are driven by amplifiers
that buffer the RF VCOs and IF VCO, respectively. The
RF output amplifier receives its input from either the
RF1 or RF2 VCO, depending upon which N-Divider
register was last written to. For example, programming
the N-Divider register for RF1 automatically selects the
RF1 VCO output.
The RFOUT pin must be coupled to its load through an
ac coupling capacitor. A matching network is required to
maximize power delivered into a 50 Ω load. The
network consists of a 2 nH series inductance, which can
be realized with a PC board trace, connected between
the RFOUT pin and the ac coupling capacitor.
The network is made to provide an adequate match to
an external 50 Ω load for both the RF1 and RF2
frequency bands. The matching network also filters the
output signal to reduce harmonic distortion. A 50 Ω load
is not required for proper operation of the Si4133G-X2.
Depending on transceiver requirements, the matching
network may not be required. See Figure 16 below.
The IFOUT pin must also be coupled to its load through
an ac coupling capacitor. A matching network is also
required to drive a 50 Ω load. See Figure 17 below.
programmed
RFOUT
Figure 16. RFOUT 50 Ω Test Circuit
frequency
2 nH
Si4133G-X2
until
560 pF
the
synthesized
50 Ω
17