MPC9229AC Freescale Semiconductor, MPC9229AC Datasheet - Page 8

• Manufacturer Part Number: MPC9229AC
• Description: IC PECL CLOCK SYNTHESIZER 32LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock/Frequency Synthesizer, Clock Generatorr

Specifications of MPC9229AC

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MPC9229
Power Supply Filtering
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCC_PLL pin impacts the device characteristics. The
MPC9229 provides separate power supplies for the digital
circuitry (VCC) and the internal PLL (VCC_PLL) of the device.
The purpose of this design technique is to try and isolate the
high switching noise digital outputs from the relatively
sensitive internal analog phase–locked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system environment
where it is more difficult to minimize noise on the power
supplies a second level of isolation may be required. The
simplest form of isolation is a power supply filter on the
VCC_PLL pin for the MPC9229. Figure 5 illustrates a typical
power supply filter scheme. The MPC9229 is most susceptible
to noise with spectral content in the 1 kHz to 1 MHz range.
Therefore, the filter should be designed to target this range.
The key parameter that needs to be met in the final filter design
is the DC voltage drop that will be seen between the VCC
supply and the MPC9229 pin of the MPC9229. From the data
sheet, the VCC_PLL current (the current sourced through the
VCC_PLL pin) is maximum 20 mA, assuming that a minimum
of 2.835 V must be maintained on the VCC_PLL pin. The
resistor shown in Figure 5 must have a resistance of 10-15 Ω
to meet the voltage drop criteria. The RC filter pictured will
provide a broadband filter with approximately 100:1
attenuation for noise whose spectral content is above 20 kHz.
As the noise frequency crosses the series resonant point of an
individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Generally, the resistor/capacitor
filter will be cheaper, easier to implement and provide an
adequate level of supply filtering. A higher level of attenuation
can be achieved by replacing the resistor with an appropriate
valued inductor. A 1000 µH choke will show a significant
impedance at 10 kHz frequencies and above. Because of the
current draw and the voltage that must be maintained on the
VCC_PLL pin, a low DC resistance inductor is required (less
than 15 Ω).
MOTOROLA
The MPC9229 is a mixed analog/digital product. Its analog
S_CLOCK
S_LOAD
P_LOAD
S_DATA
M[8:0]
N[1:0]
M, N
Freescale Semiconductor, Inc.
For More Information On This Product,
First
Figure 4. Serial Interface Timing Diagram
T2
Bit
T1
Go to: www.freescale.com
T0
N1
N0
8
M8
Layout Recommendations
rates and thus a good power supply bypassing scheme is a
must. Figure 6 shows a representative board layout for the
MPC9229. There exists many different potential board layouts
and the one pictured is but one. The important aspect of the
layout in Figure 6 is the low impedance connections between
VCC and GND for the bypass capacitors. Combining good
quality general purpose chip capacitors with good PCB layout
techniques will produce effective capacitor resonances at
frequencies adequate to supply the instantaneous switching
current for the MPC9229 outputs. It is imperative that low
inductance chip capacitors are used; it is equally important
that the board layout does not introduce back all of the
inductance saved by using the leadless capacitors. Thin
interconnect traces between the capacitor and the power
plane should be avoided and multiple large vias should be
used to tie the capacitors to the buried power planes. Fat
interconnect and large vias will help to minimize layout
induced inductance and thus maximize the series resonant
point of the bypass capacitors. Note the dotted lines circling
the crystal oscillator connection to the device. The oscillator is
a series resonant circuit and the voltage amplitude across the
crystal is relatively small. It is imperative that no actively
switching signals cross under the crystal as crosstalk energy
coupled to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the on–board oscillator. Although the MPC9229
has several design features to minimize the susceptibility to
The MPC9229 provides sub–nanosecond output edge
M7
V
CC
M6
Figure 5. V
C
1
, C
M5
2
= 0.01...0.1 µF
R
F
M4
C
= 10- - 15 Ω
F
CC PLL
= 22 µF
M3
M2
Power Supply Filter
M1
C
C
2
1
Last
M0
Bit
TIMING SOLUTIONS
MPC9229
V
VCC_PLL
CC