MPC9772FA Freescale Semiconductor, MPC9772FA Datasheet - Page 13

• Manufacturer Part Number: MPC9772FA
• Description: IC CLOCK GEN PLL LV 1:12 52-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of MPC9772FA

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:12
• Differential - Input:output: No/No
• Frequency - Max: 240MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 240MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9772 output buffer is more than
sufficient to drive 50Ω transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta of
only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used
exclusively to maintain the tight output-to-output skew of the
MPC9772. The output waveform in Figure 13. “Single versus
Dual Line Termination Waveforms” shows a step in the
waveform, this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the 36Ω
series resistor plus the output impedance does not match the
parallel combination of the line impedances. The voltage wave
launched down the two lines will equal:
reflection coefficient, to 2.6V. It will then increment towards the
TIMING SOLUTIONS
At the load end the voltage will double, due to the near unity
IN
IN
The waveform plots in Figure 13. “Single versus Dual Line
Figure 12. Single versus Dual Transmission Lines
MPC9772
MPC9772
OUTPUT
OUTPUT
BUFFER
BUFFER
14Ω
14Ω
V
Z
R
R
V
0
L
L
S
0
= 50Ω || 50Ω
= V
= 3.0 ( 25 ÷ (18+17+25)
= 1.31V
= 14Ω
= 36Ω || 36Ω
S
(Z
R
R
R
0
S
S
S
÷ (R
= 36Ω
= 36Ω
= 36Ω
Generator
Z = 50Ω
Pulse
S
+R
0
Freescale Semiconductor, Inc.
+Z
Z
Z
Z
O
O
O
For More Information On This Product,
= 50Ω
= 50Ω
0
= 50Ω
))
Figure 15. CCLK MPC9772 AC Test Reference
Go to: www.freescale.com
Z
O
R
= 50Ω
T
OutA
OutB0
OutB1
= 50Ω
V
TT
13
MPC9772 DUT
quiescent 3.0V in steps separated by one round trip delay (in
this case 4.0ns).
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 14. “Optimized Dual Line Termination” should be
used. In this case the series terminating resistors are reduced
such that when the parallel combination is added to the output
buffer impedance the line impedance is perfectly matched.
Since this step is well above the threshold region it will not
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 14. Optimized Dual Line Termination
Figure 13. Single versus Dual Waveforms
MPC9772
OUTPUT
BUFFER
14Ω
t
2
In
D
14Ω + 22Ω || 22Ω = 50Ω || 50Ω
= 3.8956
OutA
Z
O
4
= 50Ω
R
R
25Ω = 25Ω
S
S
R
= 22Ω
= 22Ω
6
T
= 50Ω
TIME (ns)
t
D
= 3.9386
OutB
8
V
TT
Z
Z
O
O
= 50Ω
= 50Ω
10
12
MPC9772
MOTOROLA
14