MPC9772FA Freescale Semiconductor, MPC9772FA Datasheet - Page 12

• Manufacturer Part Number: MPC9772FA
• Description: IC CLOCK GEN PLL LV 1:12 52-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of MPC9772FA

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:12
• Differential - Input:output: No/No
• Frequency - Max: 240MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 240MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MOTOROLA
Table 12. Confidence Factor CF
and can be used to fine-tune the effective delay through each
device.
and I/O jitter, using Figure 9 to Figure 11 to predict a maximum
I/O jitter and the specified t
reference frequency results in a precise timing performance
analysis.
factor of 99.7% (± 3σ) is assumed, resulting in a worst case
timing uncertainty from the common input reference clock to
any output of –455 ps to +455 ps relative to CCLK (PLL
feedback = ÷8, reference frequency = 50 MHz, VCO
frequency = 400 MHz, I/O jitter = 13 ps rms max., static phase
offset t
t
t
MPC9772
SK(PP)
SK(PP)
The feedback trace delay is determined by the board layout
Due to the frequency dependence of the static phase offset
In the following example calculation an I/O jitter confidence
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
CF
160
140
120
100
80
60
40
20
(∅)
0
=
=
200
= ± 166 ps):
FB=÷32
FB=÷4
[-166ps...166ps] + [-250ps...250ps] +
[(13ps ⋅ –3)...(13ps ⋅ 3)] + t
[-455ps...455ps] + t
Figure 9. MPC9772 I/O Jitter
250
Max. I/O Phase Jitter versus Frequency
FB=÷16
Parameter: PLL Feedback Divider FB
FB=÷8
Probability of Clock Edge
300
VCO Frequency [MHz]
within the Distribution
(∅
)
parameter relative to the input
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
PD, LINE(FB)
350
Freescale Semiconductor, Inc.
PD, LINE(FB)
400
For More Information On This Product,
450
Go to: www.freescale.com
480
12
Driving Transmission Lines
signals in a terminated transmission line environment. To
provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 20Ω the drivers can drive
either parallel or series terminated transmission lines. For more
information on transmission lines the reader is referred to
Motorola application note AN1091. In most high performance
clock networks point-to-point distribution of signals is the
method of choice. In a point-to-point scheme either series
terminated or parallel terminated transmission lines can be
used. The parallel technique terminates the signal at the end of
the line with a 50Ω resistance to V
thus only a single terminated line can be driven by each output
of the MPC9772 clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can drive
multiple series terminated lines. Figure 12. “Single versus Dual
Transmission Lines” illustrates an output driving a single series
terminated line versus two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC9772 clock
driver is effectively doubled due to its capability to drive multiple
lines.
The MPC9772 clock driver was designed to drive high speed
This technique draws a fairly high level of DC current and
140
120
100
120
100
80
60
40
20
80
60
40
20
0
0
200
200
FB=÷12
Figure 10. MPC9772 I/O Jitter
Max. I/O Phase Jitter versus Frequency
Figure 11. MPC9772 I/O Jitter
250
250
Parameter: PLL Feedback Divider FB
FB=÷24
FB=÷6
Max. I/O Phase Jitter versus Frequency
Parameter: PLL Feedback Divider FB
FB=÷20
FB=÷10
FB=÷40
VCO Frequency [MHz]
300
300
VCO Frequency [MHz]
350
350
CC
÷2.
400
400
TIMING SOLUTIONS
450
450
480
480