CY2304SI-1 Cypress Semiconductor Corp, CY2304SI-1 Datasheet - Page 2

• Manufacturer Part Number: CY2304SI-1
• Description: IC CLK ZDB 4OUT 133MHZ 8SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of CY2304SI-1

• Number Of Circuits: 1
• Package / Case: 8-SOIC (3.9mm Width)
• Pll: Yes
• Input: Clock
• Output: Clock
• Ratio - Input:output: 1:4
• Differential - Input:output: No/No
• Frequency - Max: 133.3MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 133MHz
• Output Frequency Range: 10 MHz to 133.3 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 2. Pin Definitions - 8-Pin SOIC
Zero Delay and Skew Control
To close the feedback loop of the CY2304, the FBK pin can be driven from any of the four available output pins. The output driving
the FBK pin is driving a total load of 7 pF, with any additional load that it drives. The relative loading of this output (with respect to the
remaining outputs) can adjust the input-output delay. This is shown in
For applications requiring zero input-output delay, all outputs including the one providing feedback must be equally loaded. If
input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and
remaining outputs.
For zero output-output skew, be sure to load outputs equally. For further information on using CY2304, refer to the application note
AN1234
Document #: 38-07247 Rev. *E
l
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
Figure 2. REF. Input to CLKA/CLKB Delay vs. Difference in Loading Between FBK Pin and CLKA/CLKB Pins
Pin
“CY2308: Zero Delay Buffer.”
1
2
3
4
5
6
7
8
CLKA1
CLKA2
CLKB1
CLKB2
Signal
REF
GND
FBK
V
DD
[1]
[2]
[2]
[2]
[2]
Input reference frequency, 5V tolerant input
Clock output, Bank A
Clock output, Bank A
Ground
Clock output, Bank B
Clock output, Bank B
3.3V supply
PLL feedback input
Figure
2.
Description
CY2304
Page 2 of 9
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