CY2304SI-1 Cypress Semiconductor Corp, CY2304SI-1 Datasheet

CY2304SI-1

Manufacturer Part Number

CY2304SI-1

Description

IC CLK ZDB 4OUT 133MHZ 8SOIC

Manufacturer

Cypress Semiconductor Corp

Type

Fanout Distribution, Zero Delay Bufferr

Datasheet

1.CY2304SC-2.pdf (9 pages)

Specifications of CY2304SI-1

Number Of Circuits

Package / Case

8-SOIC (3.9mm Width)

Pll

Yes

Input

Clock

Output

Clock

Ratio - Input:output

1:4

Differential - Input:output

No/No

Frequency - Max

133.3MHz

Divider/multiplier

No/No

Voltage - Supply

3 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Frequency-max

133MHz

Output Frequency Range

10 MHz to 133.3 MHz

Supply Voltage (max)

3.6 V

Supply Voltage (min)

3 V

Maximum Operating Temperature

+ 85 C

Minimum Operating Temperature

- 40 C

Mounting Style

SMD/SMT

Operating Supply Voltage

3.3 V

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY2304SI-1

Manufacturer:

Quantity:

35 978

Company:

Meier Automation Equipment Co., Limited

Part Number:

CY2304SI-1T

Manufacturer:

CYP

Quantity:

20 000

Current page: 1 of 9
Download datasheet (263Kb)

Cypress Semiconductor Corporation

Document #: 38-07247 Rev. *E

Features

■

Functional Description

The CY2304 is a 3.3V zero delay buffer designed to distribute

high-speed clocks in PC, workstation, datacom, telecom, and

other high performance applications.

The part has an on-chip phase-locked loop (PLL) that locks to

an input clock presented on the REF pin. The PLL feedback is

Table 1. Available Configurations

Pinouts

Logic Block Diagram

Zero input-output propagation delay, adjustable by

capacitive load on FBK input

Multiple configurations — see

Multiple low-skew outputs

10 MHz to 133 MHz operating range

90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz

Space-saving 8-pin 150-mil SOIC package

3.3V operation

Industrial temperature available

CY2304-1

CY2304-2

Device

REF

Table 1

Bank A or B

FBK from

Bank A

Bank B

on page 1

•

198 Champion Court

Figure 1. 8-Pin SOIC - Top View

CLKA1

CLKA2

GND

REF

PLL

Bank A Frequency

2 × Reference

required to be driven into the FBK pin, and can be obtained

from one of the outputs. The input-to-output skew is

guaranteed to be less than 250 ps, and output-to-output skew

is guaranteed to be less than 200 ps.

The CY2304 has two banks of two outputs each.

The CY2304 PLL enters a power down state when there are

no rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off, resulting in less than

25 μA of current draw.

Multiple CY2304 devices can accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is guaranteed to be less than 500 ps.

The CY2304 is available in two different configurations, as

shown in

where the output frequencies equal the reference if there is no

counter in the feedback path.

The CY2304–2 allows the user to obtain Ref and 1/2x or 2x

frequencies on each output bank. The exact configuration and

output frequencies depends on which output drives the

feedback pin.

Reference

FBK

CLKB1

CLKB2

•

Table 1

Extra Divider (-2)

San Jose

3.3V Zero Delay Buffer

on page 1. The CY2304–1 is the base part,

CA 95134-1709

CLKA1

CLKB2

CLKB1

CLKA2

FBK

Bank B Frequency

Reference/2

Revised September 18, 2008

Reference

•

CY2304

408-943-2600

[+] Feedback

Related parts for CY2304SI-1

CY2304SI-1 Summary of contents

Page 1

... CY2304-2 Bank A CY2304-2 Bank B Pinouts Cypress Semiconductor Corporation Document #: 38-07247 Rev. *E required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps. ...

Page 2

Table 2. Pin Definitions - 8-Pin SOIC Pin Signal [1] 1 REF 2 CLKA1 3 CLKA2 4 GND 5 CLKB1 6 CLKB2 FBK Zero Delay and Skew Control Figure 2. REF. Input to CLKA/CLKB Delay ...

Page 3

Maximum Ratings Supply Voltage to Ground Potential.................–0.5V to +7.0V DC Input Voltage (Except Ref) ...............–0. Input Voltage REF.............................................–0 Operating Conditions for CY2304SC-X Commercial Temperature Devices Parameter V Supply Voltage DD T Operating Temperature (Ambient Temperature) ...

Page 4

... Supply Voltage DD T Operating Temperature (Ambient Temperature Load Capacitance (below 100 MHz) L Load Capacitance (from 100 MHz to 133 MHz) C Input Capacitance IN Electrical Characteristics for CY2304SI-X Industrial Temperature Devices Parameter Description V Input LOW Voltage IL V Input HIGH Voltage IH I Input LOW Current IL ...

Page 5

... Electrical Characteristics for CY2304SI-X Industrial Temperature Devices Parameter Description I (PD mode) Power down Supply Current REF = 0 MHz DD I Supply Current DD Switching Characteristics for CY2304SI-X Industrial Temperature Devices [5] Parameter Name t Output Frequency 1 t Output Frequency 1 ÷ [4] Duty Cycle = (–1,–2) [4] t Rise Time 3 (– ...

Page 6

Switching Waveforms OUTPUT OUTPUT OUTPUT INPUT FBK FBK, Device 1 FBK, Device 2 Document #: 38-07247 Rev. *E Figure 2. Duty Cycle Timing 1.4V 1.4V 1.4V Figure 3. All Outputs Rise/Fall Time 2.0V 2.0V 0.8V 0.8V ...

Page 7

... CY2304SC–1 [6] 8-pin 150-mil SOIC - Tape and Reel CY2304SC–1T [6] 8-pin 150-mil SOIC CY2304SI–1 [6] 8-pin 150-mil SOIC- Tape and Reel CY2304SI–1T [6] 8-pin 150-mil SOIC CY2304SC–2 [6] 8-pin 150-mil SOIC- Tape and Reel CY2304SC–2T Pb-Free 8-pin 150-mil SOIC CY2304SXC–1 8-pin 150-mil SOIC - Tape and Reel CY2304SXC– ...

Page 8

Package Drawing and Dimensions 8 Lead (150 Mil) SOIC S08 4 5 0.189[4.800] 0.196[4.978] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] Document #: 38-07247 Rev. *E Figure 8. 8-Pin (150-Mil) SOIC S8 PIN DIMENSIONS IN INCHES[MM] MIN. 2. PIN ...

Page 9

... Description of Change Date 12/11/01 Change from Spec number: 38-01010 to 38-07247 03/04/02 On Pin Configuration Diagram (p.1), swapped CLKA2 and CLKA1 05/01/02 Added Operating Conditions for CY2304SI-X Industrial Temperature Devices 12/14/02 Power up requirements added to Operating Conditions Information 01/26/05 Added Lead-free Devices 09/18/08 Updated template. Added Note “Not recommended for new designs.” ...

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