CY7B991-7JI Cypress Semiconductor Corp, CY7B991-7JI Datasheet - Page 7

• Manufacturer Part Number: CY7B991-7JI
• Description: IC CLK BUFF SKEW 8OUT 32PLCC
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of CY7B991-7JI

• Pll: Yes
• Input: TTL
• Output: TTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: No/No
• Frequency - Max: 80MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Frequency-max: 80MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Electrical Characteristics
Over the Operating Range
Document Number: 38-07138 Rev. *E
Notes
V
V
V
V
V
V
V
I
I
I
I
I
I
I
I
PD
Parameter
6. For more information see
7. These inputs are normally wired to V
8. CY7B991 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs must
9. Total output current per output pairis approximated by the following expression that includes device current plus load current:
10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load
11. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
IH
IL
IHH
IMM
ILL
OS
CCQ
CCN
OH
OL
IH
IL
IHH
IMM
ILL
unconnected inputs at V
all datasheet limits are achieved.
not be shorted to GND. Doing so may cause permanent damage.
CY7B991:
CY7B992:
Where
circuit:
CY7B991:PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B992:PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1
See note 9 for variable definition.
F = frequency in MHz; C = capacitive load in pF; Z = line impedance in ohms; N = number of loaded outputs; 0, 1, or 2; FC = F < C.
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
(REF and FB inputs only)
Input LOW Voltage
(REF and FB inputs only)
Three Level Input HIGH
Voltage (Test, FS, xFn)
Three Level Input MID
Voltage (Test, FS, xFn)
Three Level Input LOW
Voltage (Test, FS, xFn)
Input HIGH Leakage Current
(REF and FB inputs only)
Input LOW Leakage Current
(REF and FB inputs only)
Input HIGH Current
(Test, FS, xFn)
Input MID Current
(Test, FS, xFn)
Input LOW Current
(Test, FS, xFn)
Output Short Circuit
Current
Operating Current Used by
Internal Circuitry
Output Buffer Current per
Output Pair
Power Dissipation per
Output Pair
I
I
CCN
CCN
= [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
= [(3.5+ 0.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1
[8]
Description
CC
“Group A Subgroup Testing”
/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t
[9]
[10]
[6]
CC
, GND, or left unconnected (actual threshold voltages vary as a percentage of V
[10]
[10]
[10]
V
V
V
V
Min ≤ V
Min ≤ V
Min ≤ V
Maximum
V
V
V
V
V
V
= GND (25
V
All Input
Selects Open
V
I
Input Selects Open, f
V
I
Input Selects Open, f
OUT
OUT
CC
CC
CC
CC
CC
CC
IN
IN
IN
CC
CCN
CCN
CCN
on page
= V
= V
= GND
= Max, V
= Max, V
= Max, V
= 0 mA
= 0 mA
= Min I
= Min, I
= Min, I
= Min, I
Test Conditions
= V
= V
= V
CC
CC
CC
CC
CC
CCQ
18.
CCQ
CCQ
/2
°
≤ Max
≤ Max
≤
C only)
OH
OH
OL
OL
IN
IN
OUT
= Max,
= Max,
= Max,
= –16 mA
= Max.
= 0.4V
= 46 mA
= 46 mA
=–40 mA
MAX
MAX
Mil/Ind
Com’l
V
CC
V
500 mV
–500
–0.5
CC
Min
–50
2.4
2.0
0.0
– 0.85
CY7B991
/2 –
V
500 mV
–200
–250
Max
0.45
CC
0.85
V
V
200
0.8
10
50
85
90
14
78
CC
CC
/2 +
CC
V
V
). Internal termination resistors hold
V
CC
CC
500 mV
V
–500
–0.5
CC
Min
1.35
–50
0.0
CC
–0.75
– 0.85
CY7B992
/2 –
–
V
500 mV
104
–200
Max
0.45
1.35
CC
0.85
V
V
200
N/A
10
50
85
90
19
CC
CC
/2 +
[11]
CY7B991
CY7B992
LOCK
Page 7 of 20
Unit
mW
time before
mA
mA
mA
μA
μA
μA
μA
μA
V
V
V
V
V
V
V
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