CY29773AXI Cypress Semiconductor Corp, CY29773AXI Datasheet - Page 6

• Manufacturer Part Number: CY29773AXI
• Description: IC CLK ZDB 14OUT 125MHZ 52TQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Multiplexer , Zero Delay Bufferr
• Series: Spread Aware™r

Specifications of CY29773AXI

• Number Of Circuits: 1
• Package / Case: 52-TQFP
• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Ratio - Input:output: 4:12
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 200MHz
• Maximum Input Frequency: 125 MHz
• Minimum Input Frequency: 5 MHz
• Output Frequency Range: 8.3 MHz to 200 MHz
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 2.375 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07573 Rev. *A
DC Electrical Specifications
AC Electrical Specifications
f
f
f
V
V
t
f
f
DC
t
t
Notes:
VCO
in
refDC
r
MAX
SCLK
r
(φ)
7. AC characteristics apply for parallel output termination of 50Ω to V
8. V
, t
, t
PP
CMR
Parameter
Parameter
f
f
by characterization and are not 100% tested.
lies within the V
CMR
Z
I
I
C
DDA
DDQ
I
I
OUT
DD
IH
IN
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
PP
VCO Frequency
Input Frequency
Input Duty Cycle
Peak-Peak Input Voltage
Common Mode Range
TCLK Input Rise/FallTime
Maximum Output Frequency
Serial Clock Frequency
Output Duty Cycle
Output Rise/Fall times
Propagation Delay (static phase
offset)
Input Current, High
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
(AC) specification. Violation of V
Description
Description
[6]
(V
(V
DD
DD
[8]
= 3.3V ± 5%, T
= 2.5V ±5%, T
CMR
or V
PP
impacts static phase offset t(φ).
LVPECL
V
AVDD only
All VDD pins except AVDD
Outputs loaded @ 100 MHz
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
÷24 Feedback
÷32 Feedback
÷40 Feedback
Bypass mode (PLL_EN = 0)
LVPECL
0.7V to 1.7V
÷2 Output
÷4 Output
÷6 Output
÷8 Output
÷10 Output
÷12 Output
÷16 Output
÷20 Output
÷24 Output
f
f
0.6V to 1.8V
TCLK to FB_IN
PCLK to FB_IN
MAX
MAX
IL
TT
. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed
= V
A
A
< 100 MHz
> 100 MHz
= –40°C to +85°C)
= –40°C to +85°C) (continued)
DD
Condition
Condition
[7]
–125
–125
Min.
Min.
33.3
16.6
12.5
6.25
33.3
16.6
12.5
47.5
200
500
100
8.3
1.2
8.3
0.1
50
25
20
10
25
50
25
20
10
45
12
–
–
–
–
–
5
0
–
–
Typ.
Typ.
225
15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
5
–
4
CMR
V
range and the input swing
DD
23.75
23.75
Max.
Max.
1000
63.3
47.5
31.6
15.8
63.3
47.5
31.6
15.8
52.5
11.8
380
200
190
125
125
100
9.5
1.0
1.0
10
18
95
38
19
75
95
38
19
20
55
8
–
–
– 0.6
CY29773
Page 6 of 13
MHz
MHz
MHz
MHz
Unit
Unit
mV
mA
mA
mA
µA
pF
ns
ns
ps
%
%
Ω
V