CY29773AXI Cypress Semiconductor Corp, CY29773AXI Datasheet
CY29773AXI
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CY29773AXI Summary of contents
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... Data Generator SCLK Output Disable 12 Circuitry SDATA INV_CLK Cypress Semiconductor Corporation Document #: 38-07573 Rev. *A 2.5V or 3.3V, 200-MHz, 12-Output Zero Description The CY29773 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29773 features one LVPECL and two LVCMOS reference clock inputs and provides 12 outputs partitioned in three banks of four outputs each ...
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Pin Description Pin Name 11 PECL_CLK 12 PECL_CLK# 9 TCLK0 10 TCLK1 44,46,48,50 QA(3:0) 32,34,36,38 QB(3:0) 16,18,21,23 QC(3:0) 29 FB_OUT 31 FB_IN 25 SYNC 6 PLL_EN 2 MR#/OE 8 TCLK_SEL 7 REF_SEL 52 VCO_SEL 14 INV_CLK 5,26,27 FB_SEL(2:0) I, ...
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Table 1. Frequency Table Feedback Output Divider VCO ÷4 Input Clock * 4 ÷6 Input Clock * 6 ÷8. Input Clock * 8 ÷10 Input Clock * 10 ÷12 Input Clock * 12 ÷16 Input Clock * 16 ÷20 Input ...
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Table 6. Function Table (FB_OUT) VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0 ...
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Absolute Maximum Conditions Parameter Description V DC Supply Voltage Operating Voltage Input Voltage Output Voltage OUT V Output termination Voltage TT LU Latch-up Immunity R Power Supply Ripple PS T Temperature, ...
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DC Electrical Specifications Parameter Description I Input Current, High IH I PLL Supply Current DDA I Quiescent Supply Current DDQ I Dynamic Supply Current DD C Input Pin Capacitance IN Z Output Impedance OUT AC Electrical Specifications Parameter Description f ...
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AC Electrical Specifications Parameter Description t Output-to-Output Skew sk(O) t Bank-to-Bank Skew sk(B) t Output Disable Time PLZ Output Enable Time PZL, ZH PLL Closed Loop Bandwidth (-3dB) ÷4 Feedback BW t Cycle-to-Cycle Jitter JIT(CC) t Period Jitter ...
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AC Electrical Specifications Parameter Description f Maximum Output Frequency MAX f Maximum Output Frequency MAX (continued) f Serial Clock Frequency SCLK DC Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase (φ) offset) ...
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VCO QA QC SYNC QA QC SYNC QC QA SYNC QA QC SYNC QC QA SYNC QA QC SYNC QA QC SYNC Power Management The individual output enable/freeze control of the CY29773 allows the user to implement unique power management ...
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Start Bit D0-D3 are the control bits for QA0-QA3, respectively D4-D7 are the control bits for QB0-QB3, respectively D8-D10 are the control bits for QC1-QC3, respectively D11 is the control bit for SYNC Pulse Generator ohm Figure ...
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... Ordering Information Part Number CY29773AI 52-pin TQFP CY29773AIT 52-pin TQFP – Tape and Reel Lead-free CY29773AXI 52-pin TQFP CY29773AXIT 52-pin TQFP – Tape and Reel Document #: 38-07573 Rev 100% Figure 7. Output Duty Cycle (DC) t SK(O) Figure 8. Output-to-Output Skew, t Package Type CY29773 ...
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... Document #: 38-07573 Rev. *A © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
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Document History Page Document Title:CY29773 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Document Number: 38-07573 REV. ECN No. Issue Date ** 129007 09/02/03 *A 404290 See ECN Document #: 38-07573 Rev. *A Orig. of Change RGL New Data Sheet ...