CY28442ZXC-2 Cypress Semiconductor Corp, CY28442ZXC-2 Datasheet
CY28442ZXC-2
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CY28442ZXC-2 Summary of contents
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... PLL2 96MSS PLL3 FIXED VTTPWR_GD#/PD SDATA I2C Logic SCLK Cypress Semiconductor Corporation Document #: 38-07691 Rev. *B Clock Generator for Intel • 96-/100-MHz Spreadable differential clock. • 33-MHz PCI clock • Low-voltage frequency select input 2 • support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • ...
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Pin Definitions Pin No. Name 1 VDD_REF 2 VSS_REF 33,32 CLKREQA#/SRCT6, CLKREQB#,SRCC6 7 VDD_PCI 6 VSS_PCI 3,4,5 PCI 8 ITP_EN/PCIF0 9 PCIF1/96_100_SEL 10 VTT_PWRGD#/PD 11 VDD_48 12 FS_A/48_M0 13 VSS_48 14,15 DOT96T, DOT96C 16 FS_B/TEST_MODE 17,18 96_100_SSC 19,20,22,23, SRCT/C 24,25,30,31 ...
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Pin Definitions (continued) Pin No. Name 48 VDDA2 49 XOUT 50 XIN 51 VSSA2 52 REF1 53 FS_C_TEST_SEL/ REF0 54 CPU_STP# 55 PCI_STP# 56 PCI2/SEL_CLKREQ I/O, PD 3.3V-tolerant input for CLKREQ pin selection/fixed 33-MHz clock output. Table 1. Frequency Select ...
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Table 3. Block Read and Block Write Protocol Block Write Protocol Bit Description 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 27:20 Byte Count ...
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Control Registers Byte 0: Control Register 0 Bit @Pup 7 1 CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 6 1 SRC[T/C SRC[T/C SRC[T/C SRC[T/C SRC[T/C SRC[T/C RESERVED Byte 1: Control Register 1 Bit ...
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Byte 3: Control Register 3 Bit @Pup RESERVED Byte 4: Control Register 4 Bit @Pup 7 0 96_100_SSC 6 0 DOT96T RESERVED ...
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Byte 5: Control Register 5 (continued) Bit @Pup 0 0 CPU[T/C]0 Byte 6: Control Register 6 Bit @Pup 7 0 TEST_SEL 6 0 TEST_MODE 5 0 RESERVED PCI, PCIF and SRC clock outputs except those set ...
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Byte 8: Control Register 8 (continued) Bit @Pup 1 0 CLKREQ RESERVED Byte 9: Control Register 9 Bit @Pup 96_100 SEL 2 1 96_100 ...
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Table 5. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap 14.31818 MHz AT Parallel The CY28442-2 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28442-2 to operate at the wrong frequency and violate the ppm ...
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CLKREQ#X SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW) All differential outputs that were stopped are to resume normal operation in a glitch-free manner. The maximum latency from the assertion to active ...
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PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. ...
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CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock ...
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PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW ...
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VDD_A = 2.0V S0 Power Off Figure 13. Clock Generator Power-up/Run State Diagram Document #: 38-07691 Rev VTT_PWRGD# = Low Delay >0.25mS S3 VDD_A = off Normal Operation VTT_PWRGD# = toggle CY28442-2 S2 Sample Inputs straps Wait for ...
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Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC Ø Dissipation, ...
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AC Electrical Specifications Parameter Description Crystal T XIN Duty Cycle DC T XIN Period PERIOD XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ L Long-term Accuracy ACC CPU at 0.7V T ...
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AC Electrical Specifications Parameter Description V Maximum Overshoot Voltage OVS V Minimum Undershoot Voltage UDS V Ring Back Voltage RB SRC T SRCT and SRCC Duty Cycle DC T 100-MHz SRCT and SRCC Period PERIOD T 100-MHz SRCT and SRCC ...
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AC Electrical Specifications Parameter Description DOT96T and DOT96C Rise and Fall R F Time T Rise/Fall Matching RFM ∆T Rise Time Variation R ∆T Fall Time Variation F V Voltage High HIGH V Voltage Low LOW V ...
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... CPU and SRC outputs Ω Figure 15. 0.7V Differential Clock Load Configuration Figure 16. Single-ended Output Signals (for AC Parameters Measurement) Ordering Information Part Number Lead-free CY28442ZXC-2 56-pin TSSOP CY28442ZXC-2T 56-pin TSSOP – Tape and Reel Document #: 38-07691 Rev Ω Ω Ω Ω Ω Package Type CY28442 ...
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... Document #: 38-07691 Rev. *B © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
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Document History Page Document Title: CY28442-2 Clock Generator for Intel Document Number: 38-07691 REV. ECN NO. Issue Date ** 237627 See ECN *A 378059 See ECN *B 390510 See ECN Document #: 38-07691 Rev. *B Alviso Chipset Orig. of ...