CY28339ZXC Cypress Semiconductor Corp, CY28339ZXC Datasheet - Page 5

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CY28339ZXC

Manufacturer Part Number
CY28339ZXC
Description
IC CLOCK SYNTHESIZER 48-TSSOP
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Spread Spectrum Clock Generatorr
Datasheet

Specifications of CY28339ZXC

Pll
Yes
Input
LVTTL, Crystal
Output
Clock
Number Of Circuits
1
Ratio - Input:output
8:16
Differential - Input:output
No/No
Frequency - Max
133MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP II
Frequency-max
133MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY28339ZXC
Manufacturer:
CY
Quantity:
3 252
Document #: 38-07507 Rev. *A
Byte 6: Silicon Signature Register
Byte 7: Reserved Register
Byte 8: Dial-a-Frequency Control Register N
Byte 9: Dial-a-Frequency Control Register R
Note:
5.
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored.
@Pup
@Pup
@Pup
@Pup
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
N6, MSB
N5
N4
N3
N2
N3
N0, LSB
R5, MSB
R4
R3
R2
R1
R0
DAF_ENB
Name
Name
Name
[5]
Name
(all bits are Read-only)
Revision = 0001
Vendor Code = 0011
Reserved. Set = 0.
These bits are for programming the PLL’s internal N register. This
access allows the user to modify the CPU frequency at very high
resolution (accuracy). All other synchronous clocks (clocks that are
generated from the same PLL, such as PCI) remain at their existing
ratios relative to the CPU clock.
Reserved. Set = 0.
These bits are for programming the PLL’s internal R register. This
access allows the user to modify the CPU frequency at very high
resolution (accuracy). All other synchronous clocks (clocks that are
generated from the same PLL, such as PCI) remain at their existing
ratios relative to the CPU clock.
R and N register mux selection. 0 = R and N values come from the ROM.
1 = data is loaded from DAF (SMBus) registers.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Description
Description
Description
Description
CY28339
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