CY28339ZXC Cypress Semiconductor Corp, CY28339ZXC Datasheet - Page 2

• Manufacturer Part Number: CY28339ZXC
• Description: IC CLOCK SYNTHESIZER 48-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Spread Spectrum Clock Generatorr

Specifications of CY28339ZXC

• Pll: Yes
• Input: LVTTL, Crystal
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 8:16
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP II
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07507 Rev. *A
Pin Definitions
47
1
2
43, 42,
39, 38
29
31
20
17, 18, 19
6
8, 9, 10, 12, 13,
14, 4, 5
35
34
36
46
37
21
30
45
24
25
26
11, 15, 28, 40, 44,
48
33
22
3, 7, 16, 27, 32,
41
23
Note:
2.
Pin Number
PCI3 is internally disabled and is not accessible.
REF0
XIN
XOUT
CPUT1,CPUC1
CPUT2, CPUC2
3V66_0
3V66_1/VCH
66IN/3V66_5
66BUFF [2:0]
/3V66 [4:2]
PCIF
PCI [0:2]
PCI [4:6]
PCI [7:8]
USB_48M
DOT_48M
S2
S1
IREF
PD#
PCI_STOP#
CPU_STOP#
VTT_PWRGD#
SDATA
SCLK
VDD_PCI,
VDD_3V66,
VDD_CPU,VDD_RE
F
VDD_48 MHz
VDD_CORE
GND_REF,
GND_PCI,
GND_3V66,
GND_IREF,
GND_CPU
GND_CORE
Name
I/O
3.3V 14.318-MHz clock output.
14.318-MHz crystal input.
14.318-MHz crystal input.
Differential CPU clock outputs.
3.3V 66-MHz clock output.
3.3V selectable through SMBus to be 66 MHz or 48 MHz.
66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from internal
VCO.
66-MHz buffered outputs from 66Input or 66-MHz clocks from internal VCO.
33 MHz clocks divided down from 66Input or divided down from 3V66; PCIF
default is free-running.
PCI clock outputs divided down from 66Input or divided down from 3V66;
PCI [7:8] are configurable as free-running PCI through SMBus.
Fixed 48-MHz clock output.
Fixed 48-MHz clock output.
Special 3.3V three-level input for Mode selection.
3.3V LVTTL inputs for CPU frequency selection.
A precision resistor is attached to this pin which is connected to the
internal current reference.
3.3V LVTTL input for Power_Down# (active LOW).
3.3V LVTTL input for PCI_STOP# (active LOW).
3.3V LVTTL input for CPU_STOP# (active LOW).
3.3V LVTTL input is a level-sensitive strobe used to determine when S[2:1]
inputs are valid and OK to be sampled (Active LOW). Once VTT_PWRGD#
is sampled LOW, the status of this input will be ignored.
SMBus-compatible SDATA.
SMBus-compatible SCLK.
3.3V power supply for outputs.
3.3V power supply for 48 MHz.
3.3V power supply for phase-locked loop (PLL).
Ground for outputs.
Ground for PLL.
Description
[2]
CY28339
Page 2 of 18
[+] Feedback