CY2291F Cypress Semiconductor Corp, CY2291F Datasheet - Page 9

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CY2291F

Manufacturer Part Number
CY2291F
Description
IC 3PLL EPROM CLOCK GEN 20-SOIC
Manufacturer
Cypress Semiconductor Corp
Type
Clock Generator, Fanout Distributionr
Datasheets

Specifications of CY2291F

Pll
Yes
Input
Clock, Crystal
Output
Clock, Crystal
Number Of Circuits
1
Ratio - Input:output
1:8
Differential - Input:output
No/No
Frequency - Max
66.6MHz, 90MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.3V, 5V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Frequency-max
66.6MHz/90MHz
For Use With
CY3093 - SOCKET ADAPTER FTG FOR CY2291F428-1457 - KIT DEV FTG PROGRAMMING KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1392

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Switching Characteristics, Industrial 3.3V
Switching Waveforms
Document #: 38-07189 Rev. *D
t
t
t
t
t
t
t
t
t
Parameter
6
7
8
9A
9B
9C
9D
10A
10B
Output Enable
Time
Skew
CPUCLK Slew
Clock Jitter
Clock Jitter
Clock Jitter
Clock Jitter
Lock Time for
CPLL
Lock Time for
UPLL and SPLL
Slew Limits
THREE-STATE
OUTPUTS
Name
OUTPUT
RELATED
OUTPUT
OE
ALL
[14]
[14]
[14]
[14]
CLK
CLK
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related outputs
12, 15]
Frequency transition rate
Peak-to-peak period jitter (t
clock period (f
Peak-to-peak period jitter (t
< f
Peak-to-peak period jitter
(16 MHz < f
Peak-to-peak period jitter (f
Lock Time from Power Up
Lock Time from Power Up
CPU PLL Slew Limits
OUT
Figure 2. All Outputs, Duty Cycle and Rise/Fall Time
< 16 MHz)
t
3
OUT
Figure 3. Output Three-State Timing
t
Figure 4. CLK Outputs Jitter and Skew
5
OUT
< 50 MHz)
< 4 MHz)
t
9A
Description
t
(continued)
2
t
9A
9B
OUT
7
CY2291I
CY2291FI
Max. – t
Max. – t
> 50 MHz)
t
1
9A
9B
t
4
min.),% of
min.) (4 MHz
[4]
[3,
Min.
1.0
t
6
8
8
< 0.25
< 0.25
< 400
< 250
< 0.5
< 0.7
< 25
Typ.
10
Max.
66.6
20.0
350
500
0.5
15
50
60
1
1
1
CY2291
Page 9 of 12
MHz/ms
MHz
MHz
Unit
ms
ms
ns
ns
ns
ps
ps
%
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