CY2291F Cypress Semiconductor Corp, CY2291F Datasheet - Page 6

• Manufacturer Part Number: CY2291F
• Description: IC 3PLL EPROM CLOCK GEN 20-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY2291F

• Pll: Yes
• Input: Clock, Crystal
• Output: Clock, Crystal
• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: No/No
• Frequency - Max: 66.6MHz, 90MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.3V, 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Frequency-max: 66.6MHz/90MHz
• For Use With: CY3093 - SOCKET ADAPTER FTG FOR CY2291F428-1457 - KIT DEV FTG PROGRAMMING KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1392

Electrical Characteristics, Industrial 3.3V
Switching Characteristics, Commercial 5.0V
Notes
Document #: 38-07189 Rev. *D
V
V
I
I
I
I
I
I
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
11. XBUF duty cycle depends on XTALIN duty cycle.
12. Measured at 1.4V.
13. Measured between 0.4V and 2.4V.
14. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application
15. CLKF is not guaranteed to be in phase with CLKA-D, even if it is referenced off the same PLL.
Parameter
IH
IL
OZ
DD
DDS
BATT
1
3
4
5
6
7
8
9A
9B
9C
9D
10A
IH
IL
note: “Jitter in PLL-Based Systems.”
Output Period
Output Duty
Cycle
Rise Time
Fall Time
Output Disable
Time
Output Enable
Time
Skew
CPUCLK Slew
Clock Jitter
Clock Jitter
Clock Jitter
Clock Jitter
Lock Time for
CPLL
HIGH-Level Input Voltage
LOW-Level Input Voltage
Input HIGH Current
Input LOW Current
Output Leakage Current
V
Industrial
V
in Shutdown Mode
V
DD
DD
BATT
Name
[11]
Supply Current
Power Supply Current
Power Supply Current V
Description
[14]
[14]
[14]
[14]
Clock output range, 5V
operation
Duty cycle for outputs, defined as t
f
Duty cycle for outputs, defined as t
f
Output clock rise time
Output clock fall time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related outputs
12, 15]
Frequency transition rate
Peak-to-peak period jitter (t
clock period (f
Peak-to-peak period jitter (t
(4 MHz < f
Peak-to-peak period jitter
(16 MHz < f
Peak-to-peak period jitter
(f
Lock Time from Power Up
OUT
OUT
OUT
[10]
[10]
> 66 MHZ
< 66 MHZ
> 50 MHz)
[9]
[9]
OUT
OUT
Except crystal pins
Except crystal pins
V
V
Three-state outputs
V
Shutdown active,
excluding V
OUT
IN
IN
DD
BATT
< 16 MHz)
< 50 MHz)
= V
= +0.5V
= V
< 4 MHz)
= 3.0V
DD
[13]
DD
Description
[13]
–0.5V
(continued)
max., 3.3V operation
BATT
9A
9B
Conditions
CY2291
CY2291F
Max. – t
Max. – t
CY2291I/CY2291FI
2
2
 t
 t
9A
9B
1
1
[12]
[12]
min.),% of
min.)
[3,
(100 MHz)
(90 MHz)
Min.
2.0
Min.
40%
45%
11.1
1.0
10
Typ.
< 0.25
< 400
< 250
< 1
< 1
< 0.5
< 0.7
Typ.
50%
50%
< 25
50
10
5
2.5
10
10
3
(76.923 kHz)
(76.923 kHz)
Max.
250
100
0.8
10
10
70
15
13000
13000
Max.
60%
55%
20.0
500
350
0.5
15
15
50
5
4
1
1
CY2291
Page 6 of 12
Unit
mA
MHz/m
A
A
A
A
A
V
V
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
%
s
[+] Feedback