AD9517-4BCPZ Analog Devices Inc, AD9517-4BCPZ Datasheet - Page 71
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AD9517-4BCPZ
Manufacturer Part Number
AD9517-4BCPZ
Description
IC CLOCK GEN 1.8GHZ VCO 48-LFCSP
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9517-4ABCPZ-RL7.pdf
(80 pages)
Specifications of AD9517-4BCPZ
Design Resources
High Performance, Dual Channel IF Sampling Receiver (CN0140)
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
1:12
Differential - Input:output
Yes/Yes
Frequency - Max
1.8GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LFCSP
Frequency-max
1.8GHz
Clock Ic Type
Clock Generator
Ic Interface Type
Serial
Frequency
1.8GHz
No. Of Outputs
12
Supply Current
100µA
Supply Voltage Range
3.135V To 3.465V
Digital Ic Case Style
LFCSP
Rohs Compliant
Yes
For Use With
AD9517-4/PCBZ - BOARD EVALUATION AD9517-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Reg.
Addr.
(Hex)
0x143
Table 58. LVPECL Channel Dividers
Reg.
Addr.
(Hex)
0x190
0x191
0x192
0x196
0x197
Bits
[2:1]
0
Bits
[7:4]
[3:0]
7
6
5
4
[3:0]
1
0
[7:4]
[3:0]
7
6
5
Name
Divider 0 low cycles
Divider 0 high cycles
Divider 0 bypass
Divider 0 nosync
Divider 0 force high
Divider 0 start high
Divider 0 phase offset
Divider 0 direct to output
Divider 0 DCCOFF
Divider 1 low cycles
Divider 1 high cycles
Divider 1 bypass
Divider 1 nosync
Divider 1 force high
Name
OUT7 LVDS output current
OUT7 power-down
Description
Set output current level in LVDS mode. This has no effect in CMOS mode.
2
0
0
1
1
Power-down output (LVDS/CMOS).
0: power on (default).
1: power off.
Description
Number of clock cycles (minus 1) of the divider input during which divider output stays
low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays
high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypass and power-down the divider; route input to divider output.
0: use divider.
1: bypass divider (default).
Nosync.
0: obey chip-level SYNC signal (default).
1: ignore chip-level SYNC signal.
Force divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
Selects clock output to start high or start low.
0: start low (default).
1: start high.
Phase offset (default = 0x0).
Connect OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.
0: OUT0 and OUT1 are connected to Divider 0 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enable duty-cycle correction (default).
1: disable duty-cycle correction.
Number of clock cycles of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays
high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypass and power-down the divider; route input to divider output.
0: use divider (default).
1: bypass divider.
Nosync.
0: obey chip-level SYNC signal (default).
1: ignore chip-level SYNC signal.
Force divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
1
0
1
0
1
Rev. B | Page 71 of 80
Current (mA)
1.75
3.5
5.25
7
Recommended Termination (Ω)
100
100 (default)
50
50
AD9517-4