AD9517-4BCPZ Analog Devices Inc, AD9517-4BCPZ Datasheet - Page 60
![IC CLOCK GEN 1.8GHZ VCO 48-LFCSP](/photos/6/50/65022/cp-48-8_sml.jpg)
AD9517-4BCPZ
Manufacturer Part Number
AD9517-4BCPZ
Description
IC CLOCK GEN 1.8GHZ VCO 48-LFCSP
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9517-4ABCPZ-RL7.pdf
(80 pages)
Specifications of AD9517-4BCPZ
Design Resources
High Performance, Dual Channel IF Sampling Receiver (CN0140)
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
1:12
Differential - Input:output
Yes/Yes
Frequency - Max
1.8GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LFCSP
Frequency-max
1.8GHz
Clock Ic Type
Clock Generator
Ic Interface Type
Serial
Frequency
1.8GHz
No. Of Outputs
12
Supply Current
100µA
Supply Voltage Range
3.135V To 3.465V
Digital Ic Case Style
LFCSP
Rohs Compliant
Yes
For Use With
AD9517-4/PCBZ - BOARD EVALUATION AD9517-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9517-4
Reg.
Addr.
(Hex)
0x016
0x017
Bits
[2:0]
[7:2]
Name
Prescaler P
STATUS pin
control
Description
Prescaler: DM = dual modulus and FD = fixed divide.
2
0
0
0
0
1
1
1
1
Select the signal that is connected to the STATUS pin.
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
6
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
1
0
1
5
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
4
0
0
0
0
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Mode
FD
FD
DM
DM
DM
DM
DM
FD
3
0
0
1
1
0
0
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Prescaler
Divide-by-1.
Divide-by-2.
Divide-by-2 (2/3 mode).
Divide-by-4 (4/5 mode).
Divide-by-8 (8/9 mode).
Divide-by-16 (16/17 mode).
Divide-by-32 (32/33 mode) (default).
Divide-by-3.
2
0
1
0
1
0
1
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev. B | Page 60 of 80
Level or
Dynamic
Signal
LVL
DYN
DYN
DYN
DYN
DYN
DYN
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
A divider output.
REF1 clock (differential reference when in differential mode).
Selected reference to PLL (differential reference when in differential mode).
(DLD) AND (status of selected reference) AND (status of VCO).
Signal at STATUS Pin
Ground (dc) (default).
N divider output (after the delay).
R divider output (after the delay).
Prescaler output.
PFD up pulse.
PFD down pulse.
Ground (dc); for all other cases of 0XXXXX not specified above.
The selections that follow are the same as REFMON.
Ground (dc).
REF2 clock (N/A in differential mode).
Unselected reference to PLL (not available in differential mode).
Status of selected reference (status of differential reference); active
high.
Status of unselected reference (not available in differential mode);
active high.
Status REF1 frequency (active high).
Status REF2 frequency (active high).
(Status REF1 frequency) AND (status REF2 frequency).
Status of VCO frequency (active high).
Selected reference (low = REF1, high = REF2).
Digital lock detect (DLD); active high.
Holdover active (active high).
LD pin comparator output (active high).
VS (PLL supply).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in differential mode).
Unselected reference to PLL (not available when in differential mode).
Status of selected reference (status of differential reference); active low.
Status of unselected reference (not available in differential mode); active low.
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
(Status of REF1 frequency) AND (status of REF2 frequency).
(DLD) AND (status of selected reference) AND (status of VCO).
Status of VCO frequency (active low).
Selected reference (low = REF2, high = REF1).
Digital lock detect (DLD) (active low).
Holdover active (active low).
LD pin comparator output (active low).