ADF4218LBRU-REEL Analog Devices Inc, ADF4218LBRU-REEL Datasheet - Page 9

• Manufacturer Part Number: ADF4218LBRU-REEL
• Description: IC PLL FREQ SYNTHESIZER 20-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF/IF)r

Specifications of ADF4218LBRU-REEL

• Rohs Status: RoHS non-compliant
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 3GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.6 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 3GHz

CIRCUIT DESCRIPTION
Reference Input Section
The reference input stage is shown in Figure 2. SW1 and SW2
are normally closed switches; SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
IF/RF Input Stage
The IF/RF input stage is shown in Figure 3. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
REV. C
RF
RF
REF
IN
IN
A
B
IN
Figure 2. Reference Input Stage
NC
Figure 3. IF/RF Input Stage
POWER-DOWN
GENERATOR
SW1
CONTROL
BIAS
NO
NC
SW3
SW2
500
50k
NC = NORMALLY CLOSED
NO = NORMALLY OPEN
1.6V
500
BUFFER
TPC 13. Charge Pump Output Characteristics
–2
–4
–6
6
4
2
0
0
AGND
AV
DD
0.5
1.0
TO R
COUNTER
IN
1.5
pin
2.0
–9–
V
CP
2.5
– V
Prescaler
The dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = BP + A). This prescaler, operating at CML levels, takes
the clock from the IF/RF input stage and divides it down to a
manageable frequency for the CMOS A and B counters. It is
based on a synchronous 4/5 core.
The prescaler is selectable. On the IF side, it can be set to either 8/9
(DB20 of the IF AB Counter Latch set to 0) or 16/17 (DB20 set
to 1). On the RF side of the ADF4217L/ADF4218L, it can be set
to 64/65 or 32/33. On the ADF4219L, the RF prescaler can be
set to 16/17 or 32/33. See Tables V, VI, VIII, and IX.
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed-
back counter. The devices are guaranteed to work when the
prescaler output is 188 MHz or less. Typically they will work
with 250 MHz output from the prescaler.
3.0
INPUT STAGE
Figure 4. Reference Input Stage, A and B Counters
FROM IF/RF
3.5
ADF4217L/ADF4218L/ADF4219L
4.0
V
I
CP
P
= 5V
= 4mA
4.5
MODULUS
CONTROL
N = BP + A
PRESCALER
5.0
P/P+1
LOAD
LOAD
B COUNTER
A COUNTER
11(13)-BIT
6(5)-BIT
TO PFD