MAX9452EHJ+T Maxim Integrated Products, MAX9452EHJ+T Datasheet

IC CLOCK GENERATOR W/VCXO 32TQFP

MAX9452EHJ+T

Manufacturer Part Number
MAX9452EHJ+T
Description
IC CLOCK GENERATOR W/VCXO 32TQFP
Manufacturer
Maxim Integrated Products
Type
Clock Generatorr
Datasheet

Specifications of MAX9452EHJ+T

Pll
Yes
Input
LVCMOS, LVDS, LVPECL
Output
LVDS
Number Of Circuits
1
Ratio - Input:output
2:2
Differential - Input:output
Yes/Yes
Frequency - Max
160MHz
Divider/multiplier
Yes/No
Voltage - Supply
2.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-TQFP Exposed Pad, 32-eTQFP, 32-HTQFP, 32-VQFP
Frequency-max
160MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The MAX9450/MAX9451/MAX9452 clock generators
provide high-precision clocks for timing in SONET/SDH
systems or Gigabit Ethernet systems. The MAX9450/
MAX9451/MAX9452 can also provide clocks for the high-
speed and high-resolution ADCs and DACs in 3G base
stations. Additionally, the devices can also be used as a
jitter attenuator for generating high-precision CLK signals.
The MAX9450/MAX9451/MAX9452 feature an integrated
VCXO. This configuration eliminates the use of an exter-
nal VCXO and provides a cost-effective solution for gen-
erating high-precision clocks. The MAX9450/MAX9451/
MAX9452 feature two differential inputs and clock out-
puts. The inputs accept LVPECL, LVDS, differential sig-
nals, and LVCMOS. The input reference clocks range
from 8kHz to 500MHz.
The MAX9450/MAX9451/MAX9452 offer LVPECL, HSTL,
and LVDS outputs, respectively. The output range is up
to 160MHz, depending on the selection of crystal. The
input and output frequency selection is implemented
through the I
MAX9451/MAX9452 feature clock output jitter less than
0.8ps RMS (in a 12kHz to 20MHz band) and phase-
noise attenuation greater than -130dBc/Hz at 100kHz.
The phase-locked loop (PLL) filter can be set externally,
and the filter bandwidth can vary from 1Hz to 20kHz.
The MAX9450/MAX9451/MAX9452 feature an input
clock monitor with a hitless switch. When a failure is
detected at the selected reference clock, the device
can switch to the other reference clock. The reaction to
the recovery of the failed reference clock can be
revertive or nonrevertive. If both reference clocks fail,
the PLL retains its nominal frequency within a range of
±20ppm at +25°C.
The MAX9450/MAX9451/MAX9452 operate from 2.4V to
3.6V supply and are available in 32-pin TQFP packages
with exposed pads.
19-0547; Rev 3; 11/07
SPI is a trademark of Motorola, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
SONET/SDH Systems
10 Gigabit Network Routers and Switches
3G Cellular Phone Base Stations
General Jitter Attenuation
2
C or SPI™ interface. The MAX9450/
________________________________________________________________ Maxim Integrated Products
General Description
Applications
High-Precision Clock Generators
♦ Integrated VCXO Provides a Cost-Effective
♦ 8kHz to 500MHz Input Frequency Range
♦ 15MHz to 160MHz Output Frequency Range
♦ I
♦ PLL Lock Range > ±60ppm
♦ Two Differential Outputs with Three Types of
♦ Input Clock Monitor with Hitless Switch
♦ Internal Holdover Function within ±20ppm of the
♦ Low Output CLK Jitter: < 0.8ps RMS in the 12kHz
♦ Low Phase Noise > -130dBc at 100kHz, > -140dBc
Note: All devices are specified over the -40°C to +85°C
temperature range.
For lead-free packages, contact factory.
*EP = Exposed paddle.
MAX9450EHJ
MAX9451EHJ
MAX9452EHJ
with Integrated VCXO
Solution for High-Precision Clocks
Frequency Selection
Signaling: LVPECL, LVDS, or HSTL
Nominal Frequency
to 20MHz Band
at 1MHz
2
C or SPI Programming for the Input and Output
GNDA
V
PART
V
LP1
LP2
DDA
TOP VIEW
DD
X1
X2
RJ
25
28
29
30
31
26
27
32
24
1
32 TQFP-EP*
32 TQFP-EP*
32 TQFP-EP*
PIN-PACKAGE
23
2
(5mm x 5mm)
22
Ordering Information
3
EXPOSED PAD
MAX9450
MAX9451
MAX9452
TQFP
(GND)
21
4
Pin Configuration
20
5
19
6
OUTPUT
LVPECL
18
HSTL
LVDS
7
17
8
Features
16
15 AD1
14
13
12
11
10
9
PKG CODE
SDA
CMON
AD0
SCL
GND/CS
MR
INT
H32E-6
H32E-6
H32E-6
1

Related parts for MAX9452EHJ+T

MAX9452EHJ+T Summary of contents

Page 1

... Gigabit Network Routers and Switches 3G Cellular Phone Base Stations General Jitter Attenuation SPI is a trademark of Motorola, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. High-Precision Clock Generators with Integrated VCXO ♦ ...

Page 2

High-Precision Clock Generators with Integrated VCXO ABSOLUTE MAXIMUM RATINGS V to GND ...........................................................-0.3V to +4. GNDA ......................................................-0.3V to +4.0V DDA All Other Pins to GND ...................................-0. Short-Circuit Duration (all pins) ..................................Continuous Continuous Power Dissipation (T ...

Page 3

DC ELECTRICAL CHARACTERISTICS (continued 2.4V to 3.6V, and V DDA DD DDQ V = 3.3V, and V = 1.5V for MAX9451, T DDQ DDQ PARAMETER Output Offset Voltage Change in V Between OS Complementary ...

Page 4

High-Precision Clock Generators with Integrated VCXO 2 SERIAL I C-COMPATIBLE INTERFACE TIMING CHARACTERISTICS ( 2.4V to 3.6V -40°C to +85°C. See Figure 4 for the timing parameters definition.) PARAMETER Serial Clock Bus Free Time Between ...

Page 5

3.3V +25°C, unless otherwise noted.) DD DDA DDQ A V AND V SUPPLY CURRENT DD DDA vs. VOLTAGE (MAX9450 +25° -40° ...

Page 6

High-Precision Clock Generators with Integrated VCXO PIN NAME LOCK Lock Indicator. LOCK goes low when the PLL locks. LOCK is high when the PLL is not locked. 1 INO_ and IN1_ Select Inputs. Drive SEL0 high to activate IN0; drive ...

Page 7

RJ LOCK IN0+ IN0- 0 IN1+ 1 IN1- CMON CLK INT MONITOR SEL0 SEL1 SCL PORT SDA AD0 AD1 SPI PORT GND/CS Detailed Description The MAX9450/MAX9451/MAX9452 clock generators provide high-precision clocks for timing in SONET/SDH systems or ...

Page 8

High-Precision Clock Generators with Integrated VCXO N1 and N2, respectively. CR5 and CR6 are the control function registers for output enabling, reference clock selection, and activation of the clock monitor and the holdover function. CR7 contains the status of clock ...

Page 9

CLKn output, f CLKn is the frequency of the reference clock 32,768) is the dividing factor in the feedback loop 16) are ...

Page 10

High-Precision Clock Generators with Integrated VCXO External Loop Filter When the device switches from one input reference to the other or reverts to an input reference from holdover, the output phase changes smoothly during the transition due to the narrowband ...

Page 11

Data Transfer and Acknowledge Following the START condition, each SCL clock pulse transfers 1 bit. Between a START and a STOP, multiple bytes can be transferred on the 2-wire bus. The first 7 bits (B0–B6) are for the device address. ...

Page 12

High-Precision Clock Generators with Integrated VCXO LOW HIGH SMBCLK SMBDATA t t HD:STA SU:STA A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = ...

Page 13

Table Address Setting by AD0 and AD1 AD0 AD1 Low Low Low Open Low High Open Low Open Open Open High High Low High Open High High 2 Table and SPI Register Address* ...

Page 14

High-Precision Clock Generators with Integrated VCXO Table 8. Control Registers and Control Functions CR5, CR6 FUNCTION 0: Outputs are enabled CR5[7] Output disable 1: Outputs disabled to logic-low 0: CLK0 is disabled to high impedance (overrides CR5[ setting) ...

Page 15

Table 11. Resistor Value vs. Charge-Pump Current RESISTOR (kΩ 100 150 200 Applications Information Crystal Selection The MAX9450/MAX9451/MAX9452 internal VCXO cir- cuitry requires an external crystal. The frequency of the crystal ranges from 15MHz to 160MHz, depending ...

Page 16

High-Precision Clock Generators with Integrated VCXO (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 16 ______________________________________________________________________________________ Package Information PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm, EP OPTION ...

Page 17

For the latest package outline information go to www.maxim-ic.com/packages.) ______________________________________________________________________________________ High-Precision Clock Generators with Integrated VCXO Package Information (continued) PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm, EP OPTION ...

Page 18

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products REVISION DESCRIPTION is a registered trademark of Maxim Integrated Products, Inc ...

Related keywords