NB3N3002DTR2G ON Semiconductor, NB3N3002DTR2G Datasheet - Page 4

• Manufacturer Part Number: NB3N3002DTR2G
• Description: IC CLK GEN XTAL-HCSL 16-TSSOP
• Manufacturer: ON Semiconductor
• Type: Clock Generatorr

Specifications of NB3N3002DTR2G

• Pll: Yes
• Input: Crystal
• Output: HCSL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/Yes
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
6. NB3N circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit
7. Measurement taken from differential output on single−ended channel terminated with R
8. Sampled with 20000 cycles to capture jitter component down to 100 kHz.
9. Sampled with 20000 cycles.
Table 6.
t
DUTY_CYCLE
Tjitter (TIE)
Symbol
f
is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
2 pF and current biasing resistor, R
W
CLKOUT
f
CLKIN
NOISE
Dt
OE
Dt
t
t
R
R
F
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
R
F
REF
Table 5. AC CHARACTERISTICS (V
HCSL
Driver
= 475 W
I
Clock/Crystal Input Frequency
Output Clock Frequency
Phase−Noise Performance
TIE RMS Jitter (Note 8)
Cycle−to−Cycle RMS Jitter (Note 9)
Cycle−to−Cycle Peak to Peak Jitter (Note 9)
Period RMS Jitter (Note 9)
Period Peak−to−Peak Jitter (Note 9)
Output Enable/Disable Time
Output Clock Duty Cycle (Measured at cross point)
Output Risetime (Measured from 175 mV to 525 mV, Figure 4)
Output Falltime (Measured from 525 mV to 175 mV, Figure 4)
Output Risetime Variation (Single−Ended)
Output Falltime Variation (Single−Ended)
REF
Figure 3. Typical Termination for Output Driver and Device Evaluation
33.2 W
33.2 W
R
R
L
L
=
=
REF
, from I
Characteristic
DD
REF
= 3.3 V ±5%, GND = 0 V, T
(Pin 9) to GND of 475 W. See Figures 3 and 4.
Z
Z
o
o
= 50 W
= 50 W
@ 100 kHz offset from carrier
@ 10 MHz offset from carrier
http://onsemi.com
@ 100 Hz offset from carrier
@ 10 kHz offset from carrier
@ 1 MHz offset from carrier
@ 1 kHz offset from carrier
4
f
f
f
f
f
f
CLKout
CLKout
CLKout
CLKout
CLKout
CLKout
= 200 MHz
= 200 MHz
= 200 MHz
= 200 MHz
= 200 MHz
= 200 MHz
A
= −40°C to +85°C; Note 7)
R
L
S
= 49.9 W
= 33.2 W, R
Min
175
175
25
45
L
= 49.9 W, with load capacitance of
−103
−122
−130
−138
−149
−118
Typ
340
340
2.5
1.5
25
20
10
50
R
2
49.9 W
L
=
Receiver
Max
200
125
125
1.0
700
700
35
20
55
5
3
dBc/Hz
MHz
MHz
Unit
ps
ms
ps
ps
ps
ps
%