SI5326A-C-GM Silicon Laboratories Inc, SI5326A-C-GM Datasheet - Page 11

• Manufacturer Part Number: SI5326A-C-GM
• Description: IC ANY-RATE MULTI/ATTEN 36-QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5326A-C-GM

• Package / Case: 36-QFN
• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.4GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.71 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 1.4GHz
• Max Input Freq: 710 MHz
• Max Output Freq: 945 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Outputs: 2
• Supply Current: 251 mA
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 4. AC Specifications
(V
Single-Ended Reference Clock Input Pin XA (XB with cap to GND)
Input Resistance
Input Voltage Swing
Differential Reference Clock Input Pins (XA/XB)
Input Voltage Swing
CKINn Input Pins
Input Frequency
Input Duty Cycle
(Minimum Pulse
Width)
Input Capacitance
Input Rise/Fall Time
CKOUTn Output Pins
(See ordering section for speed grade vs frequency limits)
Output Frequency
(Output not config-
ured for CMOS or
Disabled)
Maximum Output
Frequency in CMOS
Format
Output Rise/Fall
(20–80 %) @
622.08 MHz output
Output Rise/Fall
(20–80%) @
212.5 MHz output
DD
= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T
Parameter
XA/XB
CKO
CKO
Symbol
CKN
CKN
CKN
XA
XA
CKN
CKO
CKO
VPP
RIN
TRF
TRF
TRF
CIN
DC
VPP
F
F
F
RATE[1:0] = LM, ML, MH,
RATE[1:0] = LM, ML, MH,
RATE[1:0] = LM, ML, MH,
Output not configured for
A
limitation applies only
Whichever is smaller
= –40 to 85 °C)
(i.e., the 40% / 60%
CMOS or Disabled
or HM, ac coupled
or HM, ac coupled
to high frequency
Test Condition
CMOS Output
C
See Figure 2
See Figure 2
V
LOAD
20–80%
DD
clocks)
N1 = 5
N1 = 4
N1  6
or HM
= 1.71
= 5 pF
Rev. 1.0
1.213
0.002
0.002
Min
970
0.5
0.5
40
—
—
—
—
—
—
2
Typ
230
12
—
—
—
—
—
—
—
—
—
—
—
—
212.5
1134
Max
710
945
350
1.2
1.2
1.4
—
60
—
11
3
8
Si5326
each.
MHz
MHz
MHz
MHz
Unit
GHz
V
V
k
pF
ns
ns
ps
ns
%
PP
PP
,
11