SI5367A-B-GQ Silicon Laboratories Inc, SI5367A-B-GQ Datasheet - Page 2
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SI5367A-B-GQ
Manufacturer Part Number
SI5367A-B-GQ
Description
IC UP-PROG CLK MULTIPLR 100TQFP
Manufacturer
Silicon Laboratories Inc
Type
Clock Multiplierr
Specifications of SI5367A-B-GQ
Package / Case
100-TQFP, 100-VQFP
Pll
Yes with Bypass
Input
Clock
Output
CML, CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
4:5
Differential - Input:output
Yes/Yes
Frequency - Max
1.4GHz
Divider/multiplier
No/Yes
Voltage - Supply
1.62 V ~ 2.75 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Frequency-max
1.4GHz
Mounting Style
SMD/SMT
Number Of Outputs
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI5367A-B-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Si5367
Table 1. Performance Specifications
(V
2
Temperature Range
Supply Voltage
Supply Current
Input Clock Frequency
(CKIN1, CKIN2, CKIN3,
CKIN4)
Output Clock Frequency
(CKOUT1, CKOUT2,
CKOUT3, CKOUT4,
CKOUT5)
Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4)
Differential Voltage Swing CKN
Common Mode Voltage
Rise/Fall Time
Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5)
Common Mode
Differential Output Swing
Single Ended Output
Swing
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Duty Cycle
DD
= 1.8 or 2.5 V ±10%, T
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
Parameter
A
= –40 to 85 ºC)
CKN
Symbol
CKN
CKN
CK
V
V
CK
V
V
I
OCM
T
DD
DD
OD
SE
A
OF
VCM
DPP
TRF
F
DC
Manual at
dividers. Consult Silicon Labo-
ratories configuration software
multiplication ratio determined
DSPLLsim or Any-Rate Preci-
sion Clock Family Reference
settings for a given input fre-
by programming device PLL
ing
quency/clock multiplication
Input frequency and clock
Only CKOUT1 enabled
Only CKOUT1 enabled
LVPECL format output
CMOS format output
to determine PLL divider
All CKOUTs enabled
All CKOUTs enabled
Tristate/Sleep Mode
f
OUT
f
ratio combination.
Whichever is less
OUT
Test Condition
Preliminary Rev. 0.3
1.8 V ±10%
2.5 V ±10%
100 Ω load
line-to-line
www.silabs.com/tim-
= 622.08 MHz
LVPECL
20–80%
= 19.44 MHz
V
1213
2.25
1.62
0.25
Min
–40
970
1.42
0.9
1.0
DD
1.1
0.5
10
10
40
50
—
—
—
—
—
—
–
TBD
Typ
394
253
278
229
2.5
1.8
25
—
—
—
—
—
—
—
—
—
—
—
—
—
707.35
V
1417
1134
Max
2.75
1.98
TBD
0.93
435
284
321
261
945
1.25
1.9
1.4
1.7
DD
1.9
85
60
11
–
MHz
MHz
Unit
V
mA
mA
mA
mA
mA
ºC
ns
ns
%
V
V
V
V
V
V
V
PP