CY7B994V-5BBCT Cypress Semiconductor Corp, CY7B994V-5BBCT Datasheet - Page 8

• Manufacturer Part Number: CY7B994V-5BBCT
• Description: IC CLK BUFF 18OUT 200MHZ 100LBGA
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Buffer, Fanout Distributionr
• Series: RoboClock™r

Specifications of CY7B994V-5BBCT

• Number Of Circuits: 1
• Package / Case: 100-LBGA
• Pll: Yes
• Input: LVPECL, LVTTL
• Output: LVTTL
• Ratio - Input:output: 4:18
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 200MHz
• Maximum Input Frequency: 200 MHz
• Minimum Input Frequency: 24 MHz
• Output Frequency Range: 24 MHz to 200 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.97 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Output Disable Description
The feedback Divide and Phase Select Matrix Bank has two
outputs, and each of the four Divide and Phase Select Matrix
Banks have four outputs. The outputs of each bank can be
independently put into a HOLD-OFF or high impedance state.
The combination of the OUTPUT_MODE and DIS[1:4]/FBDIS
inputs determines the clock outputs’ state for each bank. When
the DIS[1:4]/FBDIS is LOW, the outputs of the corresponding
bank is enabled. When the DIS[1:4]/FBDIS is HIGH, the outputs
for that bank is disabled to a high impedance (High Z) or
HOLD-OFF state depending on the OUTPUT_MODE input.
Table 6
The HOLD-OFF state is intended to be a power saving feature.
An output bank is disabled to the HOLD-OFF state in a maximum
of six output clock cycles from the time when the disable input
(DIS[1:4]/FBDIS) is HIGH. When disabled to the HOLD-OFF
Document #: 38-07127 Rev. *I
(N/A)
Note
(N/A)
(N/A)
1F[1:0]
2F[1:0]
(N/A)
(N/A)
(N/A)
MM
4. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).
LM
LH
ML
MH
HL
HM
LL
HH
defines the disabled output functions.
(N/A)
(N/A)
(N/A)
(N/A)
(N/A)
(N/A)
(N/A)
(N/A)
3F[1:0]
4F[1:0]
MM
HL
LL
LM
HM
LH
HH
REFInput
FBInput
+1t
+2t
+3t
+6t
+7t
+8t
–2t
+4t
–8t
–7t
–6t
–4t
–3t
–1t
0t
Figure 3. Typical Outputs with FB Connected to a Zero-Skew Output
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
state, non-inverting outputs are driven to a logic LOW state on
its falling edge. Inverting outputs are driven to a logic HIGH state
on its rising edge. This ensures the output clocks are stopped
without glitch. When a bank of outputs is disabled to High Z state,
the respective bank of outputs go High Z immediately.
Table 6. DIS[1:4]/FBDIS Pin Functionality
OUTPUT_MODE
HIGH/LOW
HIGH
LOW
MID
DIS[1:4]/FBDIS
CY7B993V, CY7B994V
HIGH
HIGH
LOW
X
[]
RoboClock
FACTORY TEST
Output Mode
HOLD-OFF
ENABLED
HIGH Z
Page 8 of 18
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