ICS527R-01I IDT, Integrated Device Technology Inc, ICS527R-01I Datasheet - Page 6

• Manufacturer Part Number: ICS527R-01I
• Description: IC CLOCK SLICER ZD BUFFER 28SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of ICS527R-01I

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 140MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Frequency-max: 140MHz
• Number Of Elements: 1
• Pll Input Freq (min): 600KHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: QSOP
• Output Frequency Range: 4 to 140MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 527R-01I

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 6
ICS527-01
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
125 MHz
125 MHz,
25 MHz,
50 MHz,
25 MHz
QA0-7
QB0-7
VDD
Using the equation for selecting dividers gives:
If FDW = 0, then RDW = 8. This gives the required divide-by-5 function. Setting pin DIV2 = 1 gives both a
25 MHz and a 50 MHz output from the ICS527-01. The FBIN pin is connected to the QA7 output of the
MK74CB218. This aligns all the outputs of the MK74CB218 with the 25 MHz input since the ICS527-01
aligns rising edges on the ICLK and FBIN pins. The propagation delay of the buffer is compensated by the
PLL.
In this example, series termination resistors have been omitted for clarity but should be used on all clock
outputs.
25 MHz = 125 MHz x
ICLK
0.01 F
The layout design above produces the waveforms shown below.
R5
R6
DIV2
S0
S1
VDD
ICLK
GND
OECLK2
2XDRIVE
F0
F1
F2
FBIN
(FDW + 2)
(RDW + 2)
Note: Series terminating resistors are not shown.
CLK1
CLK2
PDTS
GND
VDD
R4
R3
R2
R1
R0
F6
F5
F4
F3
0.01 F
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No via’s should be used
0.01 F
QA4
GND
INA
QA0
QA1
QA2
VDD
VDD
QA3
GND
QA5
QA6
QA7
OE
ZDB AND MULTIPLIER/DIVIDER
GND
GND
VDD
VDD
VDD
QB0
QB1
QB2
QB3
QB4
QB5
QB6
QB7
INB
0.01 F
0.01 F
ICS527-01
REV G 051310