ICS527R-01I IDT, Integrated Device Technology Inc, ICS527R-01I Datasheet - Page 2

• Manufacturer Part Number: ICS527R-01I
• Description: IC CLOCK SLICER ZD BUFFER 28SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of ICS527R-01I

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 140MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Frequency-max: 140MHz
• Number Of Elements: 1
• Pll Input Freq (min): 600KHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: QSOP
• Output Frequency Range: 4 to 140MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 527R-01I

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 2
ICS527-01
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER
Pin Assignment
Pin Descriptions
2XDRIVE
OECLK2
1,2, 24-28
Number
DIV2
ICLK
FBIN
GND
VDD
12-18
6, 23
9, 20
Pin
R5
R6
4, 5
S0
S1
F0
F1
F2
10
11
19
21
22
3
7
8
28 pin 150 mil body SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2XDRIVE
OECLK2
R5, R6,
Name
S0, S1
R0-R4
F0-F6
PDTS
CLK2
CLK1
FBIN
DIV2
ICLK
GND
VDD
Pin
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Output
Output
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Pin
R4
R3
R2
R1
R0
VDD
CLK1
CLK2
GND
PDTS
F6
F5
F4
F3
Reference divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up resistor.
Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based
on the table above. Internal pull-up resistor.
Select pins for output divider determined by user. See table above. Internal
pull-up resistor.
Connect to VDD.
Reference clock input.
Feedback clock input.
Connect to ground.
CLK2 Output Enable. CLK2 tri-stated when low. Internal pull-up resistor.
Clock output drive strength doubled when high. Internal pull-up resistor.
Feedback divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up resistor.
Power Down. Active low. Turns off entire chip when low, both clock outputs are
tri-stated. Internal pull-up resistor.
Output clock 2. Can be SYNC output or a low skew divide by 2 of CLK1.
Output clock 1.
Frequency Range Table
To cover the range from 10 to 18 MHz (0 to 70°C) and 8
to 16 MHz (-40 to 85°C), select address 01 to generate
2x your desired output frequency, then configure CLK2
to generate CLK1/2.
CLK2 Operation Table
S1 S0
0
0
1
1
OECLK2
0
1
1
0
1
0
1
Commercial (0 to 70°C)
Pin Description
DIV2
X
0
1
75 -160
37 - 75
18 - 37
CLK1 Output Frequency (MHz)
4 - 10
CLK1/2
SYNC
CLK2
Z
ZDB AND MULTIPLIER/DIVIDER
CLK Drive Select Table
2XDRIVE
0
1
Industrial (-40 to 85°C)
ICS527-01
Output Drive
70 - 140
35 - 70
16 - 35
4 - 8
12 mA
25 mA
REV G 051310