ICS650R-21ILF IDT, Integrated Device Technology Inc, ICS650R-21ILF Datasheet - Page 2
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ICS650R-21ILF
Manufacturer Part Number
ICS650R-21ILF
Description
IC CLK SOURCE SYSTEM PER 20-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock/Frequency Synthesizerr
Datasheet
1.ICS650R-21LFT.pdf
(8 pages)
Specifications of ICS650R-21ILF
Pll
Yes
Input
Clock, Crystal
Output
CMOS
Number Of Circuits
1
Ratio - Input:output
1:8
Differential - Input:output
No/No
Frequency - Max
66.67MHz
Divider/multiplier
No/No
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SSOP
Frequency-max
67MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
650R-21ILF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS650R-21ILF
Manufacturer:
SMI
Quantity:
7 385
Pin Assignment
USB Clock (MHz)
Pin Descriptions
IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE
Number
ICS650-21
SYSTEM PERIPHERAL CLOCK SOURCE
Pin
10
11
12
USEL
1
2
3
4
5
6
7
8
9
M
0
1
X1/ICLK
UCLK
ACLK
USEL
GND
VDD
VDD
20M
25M
X1/ICLK
PCLK1
X2
Name
USEL
UCLK
ACLK
GND
VDD
VDD
20M
25M
Pin
OE
X2
UCLK
20-pin (150 mil) SSOP
12
24
48
10
1
2
3
4
5
6
7
8
9
Output
Output
Output
Output
Output
Power
Power
Power
Type
Input
Input
Pin
XO
XI
20
19
18
17
16
15
14
13
12
11
PSEL1
PSEL0
PCLK2
PCLK3
VDD
ASEL
GND
OFF/14.318M
PCLK1
OE
UCLK select pin. Determines frequency of USB clock per table above.
Crystal connection. Connect to parallel mode 25 MHz crystal. Leave open
for clock.
Crystal connection. Connect to parallel mode 25 MHz crystal or clock.
Connect to VDD. Must be same value as other VDD. Decouple with pin 6.
Connect to VDD. Must be same value as other VDD.
Connect to ground.
USB clock output per table above.
Fixed 20 MHz output for Ethernet.
AC97 audio clock output per table above.
Fixed 25 MHz reference output for Fast Ethernet.
Output enable. Tri-states all outputs when low.
PCLK output number 1 per table above.
2
Processor Clock (MHz)
Audio Clock (MHz)
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
PSEL1
M
M
M
Pin Description
0
0
0
1
1
1
ASEL
M
0
1
PSEL0
M
M
M
0
1
0
1
0
1
49.152
24.576
14.318
ACLK
33.3333
PCLK1
25
40
20
20
20
50
TEST MODE
TEST MODE
PCLK2, 3
66.6667
33.3333
66.6667
ICS650-21
CLOCK SYNTHESIZER
100
50
80
40
REV J 051310