ADF4156BRUZ Analog Devices Inc, ADF4156BRUZ Datasheet - Page 19

• Manufacturer Part Number: ADF4156BRUZ
• Description: IC PLL FRAC-N FREQ SYNTH 16TSSOP
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4156BRUZ

• Design Resources: Low-Noise Microwave fractional-N PLL using active loop filter and RF prescaler (CN0174)
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 6GHz
• Pll Type: Frequency Synthesis
• Frequency: 6GHz
• Supply Current: 12mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPUR MECHANISMS
This section describes the three spur mechanisms that arise
with a fractional-N synthesizer and how to minimize these
spurs in the ADF4156.
Fractional Spurs
The fractional interpolator in the ADF4156 is a third-order Σ-Δ
modulator with a modulus (MOD) that is programmable to any
integer value from 2 to 4095. In low spur mode (dither enabled),
the minimum allowable value of MOD is 50. The Σ-Δ modulator
is clocked at the PFD reference rate (f
frequencies to be synthesized at a channel step resolution of
f
In low noise mode (dither off), the quantization noise from the
Σ-Δ modulator appears as fractional spurs. The interval between
spurs is f
in the digital Σ-Δ modulator. For the third-order modulator used
in the ADF4156, the repeat length depends on the value of MOD,
as listed in Table 7.
Table 7. Fractional Spurs with Dither Off
Condition
If MOD is divisible by 2, but not 3
If MOD is divisible by 3, but not 2
If MOD is divisible by 6
Otherwise
In low spur mode (dither enabled), the repeat length is extended
to 2
PFD
/MOD.
21
cycles, regardless of the value of MOD, which makes the
PFD
Figure 22. Topology 1—Fast-Lock Loop Filter Topology
Figure 23. Topology 2—Fast-Lock Loop Filter Topology
ADF4154
ADF4154
/L, where L is the repeat length of the code sequence
MUXOUT
MUXOUT
CP
CP
R1A
C1
C1
R1
R1
R1A
C2
C2
Repeat
Length
2 × MOD
3 × MOD
6 × MOD
MOD
PFD
R2
R2
) that allows PLL output
C3
C3
Spur Interval
Channel step/2
Channel step/3
Channel step/6
Channel step
VCO
VCO
Rev. A | Page 19 of 24
quantization error spectrum look like broadband noise. As a
result, the in-band phase noise at the PLL output can be degraded
by as much as 10 dB. Therefore, for lowest noise, keeping dither
off is a better choice, particularly when the final loop bandwidth is
low enough to attenuate even the lowest frequency fractional spur.
Integer Boundary Spurs
Another mechanism for fractional spur creation is interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (as is the case
with fractional-N synthesizers), spur sidebands appear on the
VCO output spectrum at an offset frequency that corresponds
to the beat note or the difference in frequency between an
integer multiple of the reference and the VCO frequency.
These spurs are attenuated by the loop filter and are more
noticeable on channels close to integer multiples of the
reference, where the difference frequency can be inside the loop
bandwidth, hence the name integer boundary spurs.
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism that
bypasses the loop can cause a problem. One such mechanism is
feedthrough of low levels of switching noise from the on-chip
reference through the RF
in reference spur levels as high as −90 dBc. Care should be taken in
the PCB layout to ensure that the VCO is well separated from the
input reference to avoid a possible feedthrough path on the board.
SPUR CONSISTENCY AND FRACTIONAL SPUR
OPTIMIZATION
With dither off, the fractional spur pattern due to the quantization
noise of the Σ-Δ modulator also depends on the phase word set
as the starting point of the modulator. Setting the Σ-Δ reset bit
(DB14 in Register R3) to 0 ensures that this starting point is used
for the Σ-Δ modulator on every write to Register R0.
The phase word can be varied to optimize the fractional and
subfractional spur levels on any particular frequency. Therefore,
a look-up table of phase values corresponding to each frequency
can be constructed for use when programming the ADF4156.
The evaluation software has a sweep function to sweep the
phase word so that the user can observe the spur levels on a
spectrum analyzer.
If a look-up table is not used, keep the phase word at a constant
value to ensure consistent spur levels on a particular frequency.
IN
pin and back to the VCO, resulting
ADF4156