ADF4156BRUZ Analog Devices Inc, ADF4156BRUZ Datasheet
ADF4156BRUZ
Specifications of ADF4156BRUZ
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ADF4156BRUZ Summary of contents
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FEATURES RF bandwidth to 6 GHz 2 3.3 V power supply Separate V pin allows extended tuning voltage P Programmable fractional modulus Programmable charge-pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with ADF4110/ADF4111/ADF4112/ADF4113, ADF4106, ...
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ADF4156 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Specifications .................................................................. 4 Absolute Maximum Ratings ............................................................ 5 Thermal Impedance ..................................................................... 5 ESD ...
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SPECIFICATIONS 2 3 Table 1. Parameter RF CHARACTERISTICS RF Input Frequency ( REFERENCE CHARACTERISTICS REF Input Frequency IN REF Input Sensitivity IN REF Input ...
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ADF4156 TIMING SPECIFICATIONS 2 3 Table 2. Parameter Limit MIN MAX ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, GND = AGND = DGND = unless otherwise noted. Table 3. Parameter V to GND GND ...
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ADF4156 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SET CPGND 3 14 ADF4156 TOP VIEW AGND 4 13 (Not to Scale ...
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TYPICAL PERFORMANCE CHARACTERISTICS PFD = 25 MHz, loop bandwidth = 20 kHz, reference = 100 MHz, I phase noise system –5 – 4/5 –15 –20 –25 –30 –35 – ...
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ADF4156 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 11. While the device is operating, SW1 and SW2 are usually closed switches and SW3 is open. When a power-down is initiated, SW3 is closed and ...
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PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R-counter and N-counter and produces an output proportional to the phase and frequency difference between them. Figure simplified schematic of the phase frequency detector. ...
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ADF4156 REGISTER MAPS RE- MUXOUT CONTROL SERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 ...
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FRAC/INT REGISTER, R0 With the control bits (Bits[2:0]) of Register R0 set to 000, the on-chip FRAC/INT register is programmed. Figure 17 shows the input data format for programming this register. 12-Bit Integer Value (INT) These 12 bits control what ...
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ADF4156 PHASE REGISTER, R1 With the control bits (Bits[2:0]) of Register R1 set to 001, the on-chip phase register is programmed. Figure 18 shows the input data format for programming this register. 12-Bit Phase Value These 12 bits control what ...
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MOD/R REGISTER, R2 With the control bits (Bits[2:0]) of Register R1 set to 010, the on-chip MOD/R register is programmed. Figure 19 shows the input data format for programming this register. Noise and Spur Mode The noise modes on the ...
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ADF4156 NOISE CURRENT MODE SETTING DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ...
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FUNCTION REGISTER, R3 With the control bits (Bits[2:0]) of Register R2 set to 011, the on-chip function register is programmed. Figure 20 shows the input data format for programming this register. Counter Reset DB3 is the counter reset bit for ...
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ADF4156 CLK DIV REGISTER, R4 With the control bits (Bits[2:0]) of Register R3 set to 100, the on-chip clock divider register (R4) is programmed. Figure 21 shows the input data format for programming this register. 12-Bit Clock Divider Value The ...
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RF SYNTHESIZER: A WORKED EXAMPLE The following equation governs how the synthesizer should be programmed [INT + (FRAC/MOD)] × [F OUT where the RF frequency output. OUT INT is the integer division factor. FRAC is the ...
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ADF4156 In most cases, this method also provides faster lock times than the bandwidth switching mode method. In extreme cases, where cycle slips do not exist in the settling transient, the bandwidth switching mode can be used. Cycle Slip Reduction ...
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ADF4154 MUXOUT R1A Figure 22. Topology 1—Fast-Lock Loop Filter Topology ADF4154 R1A R1 MUXOUT Figure 23. Topology 2—Fast-Lock Loop Filter Topology SPUR MECHANISMS This section describes the three spur mechanisms that ...
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ADF4156 PHASE RESYNC The output of a fractional-N PLL can settle to any MOD phase offset with respect to the input reference, where MOD is the fractional modulus. The phase resync feature in the ADF4156 is used to produce a ...
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INTERFACING The ADF4156 has a simple SPI-compatible serial interface for writing to the device. CLOCK, DATA, and LE control the data transfer. When latch enable (LE) is high, the 29 bits that have been clocked into the input register on ...
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ADF4156 OUTLINE DIMENSIONS 0.15 0.05 PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 5.10 5.00 4. 4.50 6.40 4.40 BSC 4. PIN 1 1.20 MAX 0.20 0.09 8° 0.30 0° 0.65 0.19 SEATING BSC ...
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... ORDERING GUIDE Model Temperature Range 1 ADF4156BRUZ −40°C to +85°C 1 ADF4156BRUZ-RL −40°C to +85°C 1 ADF4156BRUZ-RL7 −40°C to +85°C 1 ADF4156BCPZ −40°C to +85°C 1 ADF4156BCPZ-RL −40°C to +85°C 1 ADF4156BCPZ-RL7 −40°C to +85°C 1 EVAL-ADF4156EBZ1 RoHS Compliant Part. Package Description ...
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ADF4156 NOTES 2 Purchase of licensed I C components of Analog Devices, Inc., or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Patent Rights to use these components ...