ADF4116BRU Analog Devices Inc, ADF4116BRU Datasheet - Page 21

• Manufacturer Part Number: ADF4116BRU
• Description: IC SYNTH PLL RF 550MHZ 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4116BRU

• Rohs Status: RoHS non-compliant
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 550MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 550MHz
• Number Of Elements: 1
• Supply Current: 5.5mA
• Pll Input Freq (min): 5MHz
• Pll Input Freq (max): 550MHz
• Operating Supply Voltage (typ): 3/5V
• Operating Temp Range: -40C to 85C
• Package Type: TSSOP
• Output Frequency Range: Up to 200MHz
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Pin Count: 16
• Lead Free Status / RoHS Status: Not Compliant

APPLICATIONS INFORMATION
LOCAL OSCILLATOR FOR THE
GSM BASE STATION TRANSMITTER
Figure 35 shows the ADF4117/ADF4118 being used with a
VCO to produce the LO for a GSM base station transmitter.
The reference input signal is applied to the circuit at F
in this case, is terminated in 50 Ω. A typical GSM system has a
13 MHz TCXO driving the reference input without a 50 Ω
termination. To have a channel spacing of 200 kHz (the GSM
standard), the reference input must be divided by 65, using the
on-chip reference divider of the ADF4117/ADF1118.
The charge pump output of the ADF4117/ADF1118 (Pin 2)
drives the loop filter. In calculating the loop filter component
values, a number of items need to be considered. In this example,
the loop filter was designed so that the overall phase margin for
the system is 45°. Other PLL system specifications include:
K
K
Loop bandwidth = 20 kHz
F
N = 4500
Extra reference spur attenuation = 10 dB
All of these specifications are needed and are used to produce
the loop filter component values shown in Figure 36.
The loop filter output drives the VCO, which, in turn, is fed back
to the RF input of the PLL synthesizer; it also drives the RF
output terminal. A T-circuit configuration provides 50 Ω
matching between the VCO output, the RF output, and the
RF
In a PLL system, it is important to know when the system is in
locked mode. In Figure 35, this is accomplished by using the
MUXOUT signal from the synthesizer. The MUXOUT pin can
be programmed to monitor various internal signals in the
synthesizer. One of these is the LD or lock-detect signal.
REF
D
V
IN
= 1 mA
= 12 MHz/V
= 200 kHz
terminal of the synthesizer.
REFIN
and,
Rev. D | Page 21 of 28
SHUTDOWN CIRCUIT
The attached circuit in Figure 36 shows how to shut down both
the ADF411x family and the accompanying VCO. The ADG702
switch goes open-circuit when a Logic 1 is applied to the IN
input. The low cost switch is available in both SOT-23 and
MSOP packages.
DIRECT CONVERSION MODULATOR
In some applications, a direct conversion architecture can be
used in base station transmitters. Figure 37 shows the
combination available from Analog Devices, Inc. to implement
this solution.
The circuit diagram shows the AD9761 being used with the
AD8346. The use of dual integrated DACs, such as the AD9761
with specified ±0.02 dB and ±0.004 dB gain and offset matching
characteristics, ensures minimum error contribution (over
temperature) from this portion of the signal chain.
The local oscillator is implemented by using the ADF4117/
ADF4118. In this case, the FOX801BH-130 provides the stable
13 MHz reference frequency. The system is designed for
200 kHz channel spacing and an output center frequency of
1960 MHz. The target application is a WCDMA base station
transmitter. Typical phase noise performance from this LO is
−85 dBc/Hz at a 1 kHz offset. The LO port of the AD8346 is
driven in single-ended fashion. LOIN is ac-coupled to ground
with the 100 pF capacitor, and LOIP is driven through the ac-
coupling capacitor from a 50 Ω source. An LO drive level between
−6 dBm and −12 dBm is required. The circuit in Figure 37 gives a
typical level of −8 dBm.
The RF output is designed to drive a 50 Ω load, but it must be
ac-coupled as shown in Figure 37. If the I and Q inputs are
driven in quadrature by 2 V p-p signals, the resulting output
power is approximately −10 dBm.
ADF4116/ADF4117/ADF4118