ADF4116BRU Analog Devices Inc, ADF4116BRU Datasheet - Page 12

• Manufacturer Part Number: ADF4116BRU
• Description: IC SYNTH PLL RF 550MHZ 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4116BRU

• Rohs Status: RoHS non-compliant
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 550MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 550MHz
• Number Of Elements: 1
• Supply Current: 5.5mA
• Pll Input Freq (min): 5MHz
• Pll Input Freq (max): 550MHz
• Operating Supply Voltage (typ): 3/5V
• Operating Temp Range: -40C to 85C
• Package Type: TSSOP
• Output Frequency Range: Up to 200MHz
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Pin Count: 16
• Lead Free Status / RoHS Status: Not Compliant

ADF4116/ADF4117/ADF4118
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 25. SW1 and SW2
are normally closed switches; SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
RF INPUT STAGE
The RF input stage is shown in Figure 26. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A counter
and B counter, enables the large division ratio, N, to be realized
(N = PB + A). The dual-modulus prescaler takes the CML clock
from the RF input stage and divides it down to a manageable
frequency for the CMOS A counter and CMOS B counter. The
prescaler is programmable. It can be set in software to 8/9 for the
ADF4116 and to 32/33 for the ADF4117 and ADF4118. It is based
on a synchronous 4/5 core.
RF
RF
REF
IN
IN
A
B
IN
GENERATOR
NC
Figure 25. Reference Input Stage
POWER-DOWN
BIAS
SW1
CONTROL
Figure 26. RF Input Stage
NO
NC
500Ω
SW3
SW2
100kΩ
1.6V
500Ω
BUFFER
AGND
AV
TO R COUNTER
DD
IN
pin
Rev. D | Page 12 of 28
A COUNTER AND B COUNTER
The A CMOS counter and B CMOS counter combine with the
dual-modulus prescaler to allow a wide ranging division ratio in
the PLL feedback counter. The counters are specified to work
when the prescaler output is 200 MHz or less.
Pulse Swallow Function
The A counter and B counter, in conjunction with the dual-
modulus prescaler, make it possible to generate output
frequencies that are spaced only by the reference frequency
divided by R. The equation for the VCO frequency is as follows:
where:
f
oscillator (VCO).
P is the preset modulus of dual-modulus prescaler.
B is the preset divide ratio of binary 13-bit counter (3 to 8191).
A is the preset divide ratio of binary 5-bit swallow counter (0 to 31).
f
oscillator.
R is the preset divide ratio of binary 14-bit programmable
reference counter (1 to 16,383).
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the input clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
VCO
REFIN
is the output frequency of external voltage controlled
is the output frequency of the external reference frequency
f
VCO
INPUT STAGE
FROM RF
=
[
(
P
MODULUS
CONTROL
×
N = BP + A
Figure 27. A Counter and B Counter
B
PRESCALER
)
+
P/P + 1
A
]
×
f
REFIN
/
R
LOAD
LOAD
A COUNTER
B COUNTER
13-BIT
5-BIT
TO PFD