74HC7046AD,112 NXP Semiconductors, 74HC7046AD,112 Datasheet - Page 2

• Manufacturer Part Number: 74HC7046AD,112
• Description: IC PLL W/LOCK DETECTOR 16SOIC
• Manufacturer: NXP Semiconductors
• Type: Phase Lock Loop (PLL)r
• Series: 74HCr

Specifications of 74HC7046AD,112

• Number Of Circuits: 1
• Package / Case: 16-SOIC (3.9mm Width)
• Pll: Yes
• Input: Clock
• Output: Clock
• Ratio - Input:output: 2:3
• Differential - Input:output: No/No
• Frequency - Max: 19MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Frequency-max: 19MHz
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74HC7046AD; 74HC7046AD; 933827470112

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT7046 are high-speed
Si-gate CMOS devices and are
specified in compliance with JEDEC
standard no. 7.
The 74HC/HCT7046 are
phase-locked-loop circuits that
comprise a linear voltage-controlled
oscillator (VCO) and two different
phase comparators (PC1 and PC2)
with a common signal input amplifier
and a common comparator input.
A lock detector is provided and this
gives a HIGH level at pin 1 (LD) when
the PLL is locked. The lock detector
capacitor must be connected
between pin 15 (C
(GND). The value of the C
can be determined, using information
supplied in Fig.32. The input signal
can be directly coupled to large
voltage signals, or indirectly coupled
(with a series capacitor) to small
voltage signals. A self-bias input
circuit keeps small voltage signals
within the linear region of the input
December 1990
Low power consumption
Centre frequency up to 17 MHz
(typ.) at V
Choice of two phase comparators:
EXCLUSIVE-OR;
edge-triggered JK flip-flop;
Excellent VCO frequency linearity
VCO-inhibit control for ON/OFF
keying and for low standby power
consumption
Minimal frequency drift
Operation power supply voltage
range:
VCO section 3.0 to 6.0 V
digital section 2.0 to 6.0 V
Zero voltage offset due to op-amp
buffering
Output capability: standard
I
Phase-locked-loop with lock detector
CC
category: MSI
CC
= 4.5 V
LD
) and pin 8
LD
capacitor
amplifiers. With a passive low-pass
filter, the “7046” forms a second-order
loop PLL. The excellent VCO linearity
is achieved by the use of linear
op-amp techniques.
VCO
The VCO requires one external
capacitor C1 (between C1
and one external resistor R1
(between R
external resistors R1 and R2
(between R
GND). Resistor R1 and capacitor C1
determine the frequency range of the
VCO. Resistor R2 enables the VCO
to have a frequency offset if required.
The high input impedance of the VCO
simplifies the design of low-pass
filters by giving the designer a wide
choice of resistor/capacitor ranges. In
order not to load the low-pass filter, a
demodulator output of the VCO input
voltage is provided at pin 10
(DEM
techniques where the DEM
voltage is one threshold voltage lower
than the VCO input voltage, here the
DEM
VCO input. If DEM
resistor (R
from DEM
DEM
VCO output (VCO
connected directly to the comparator
input (COMP
frequency-divider. The VCO output
signal has a duty factor of 50%
(maximum expected deviation 1%), if
the VCO input is held at a constant
DC level. A LOW level at the inhibit
input (INH) enables the VCO and
demodulator, while a HIGH level turns
both off to minimize standby power
consumption.
The only difference between the HC
and HCT versions is the input level
specification of the INH input. This
input disables the VCO section. The
comparators’ sections are identical,
so that there is no difference in the
OUT
OUT
OUT
voltage equals that of the
should be left open. The
). In contrast to conventional
OUT
S
1
1
) should be connected
IN
and GND) or two
and GND, and R
to GND; if unused,
), or connected via a
OUT
2
OUT
) can be
is used, a load
A
OUT
and C1
2
and
B
)
SIG
inputs between the HC and HCT
versions.
Phase comparators
The signal input (SIG
directly coupled to the self-biasing
amplifier at pin 14, provided that the
signal swing is between the standard
HC family input logic levels.
Capacitive coupling is required for
signals with smaller swings.
Phase comparator 1 (PC1)
This is an EXCLUSIVE-OR network.
The signal and comparator input
frequencies (f
factor to obtain the maximum locking
range. The transfer characteristic of
PC1, assuming ripple (f
suppressed,
is:
where V
output at pin 10;
V
filter).
The phase comparator gain
is:
The average output voltage from
PC1, fed to the VCO input via the
low-pass filter and seen at the
demodulator output at pin 10
(V
phase differences of signals (SIG
and the comparator input (COMP
as shown in Fig.6. The average of
V
there is no signal or noise at SIG
and with this input the VCO oscillates
at the centre frequency (f
K
V
DEMOUT
DEMOUT
p
DEMOUT
DEMOUT
IN
=
(pin 14) or COMP
V
---------- - V r .
74HC/HCT7046A
CC
DEMOUT
= V
is equal to 1/2 V
), is the resultant of the
=
PC1OUT
i
V
---------- -
) must have a 50% duty
Product specification
CC
is the demodulator
(via low-pass
SIGIN
IN
) can be
r
IN
= 2f
o
CC
). Typical
(pin 3)
–
i
when
) is
COMPIN
IN
IN
IN
)
)