CY29973AI Cypress Semiconductor Corp, CY29973AI Datasheet - Page 3

• Manufacturer Part Number: CY29973AI
• Description: IC CLK ZDB 12OUT 125MHZ 52TQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Multiplexer , Spread Spectrum Clock Generator, Zero Delay Bufferr

Specifications of CY29973AI

• Number Of Circuits: 1
• Package / Case: 52-TQFP
• Pll: Yes with Bypass
• Input: PECL
• Output: Clock
• Ratio - Input:output: 4:12
• Differential - Input:output: No/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.9 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 125MHz
• Maximum Input Frequency: 480 MHz
• Minimum Input Frequency: 200 MHz
• Output Frequency Range: 125 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.9 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Definitions
Document #: 38-07291 Rev. *C
11
12
9
10
44, 46, 48, 50 QA(3:0)
32, 34, 36, 38 QB(3:0)
16, 18, 21, 23 QC(3:0)
29
25
42, 43
40, 41
19, 20
5, 26, 27
52
31
6
7
8
2
14
3
4
17, 22, 28,
33,37, 45, 49
13
1, 15, 24, 30,
35, 39, 47, 51
Note
2. A bypass capacitor (0.1μF) must be placed as close as possible to each positive power (<0.2”). If these bypass capacitors are not close to the pins their high frequency
filtering characteristics is cancelled by the lead inductance of the traces.
Pin
PECL_CLK
PECL_CLK#
TCLK0
TCLK1
FB_OUT
SYNC
SELA(1,0)
SELB(1,0)
SELC(1,0)
FB_SEL(2:0)
VCO_SEL
FB_IN
PLL_EN
REF_SEL
TCLK_SEL
MR#/OE
INV_CLK
SCLK
SDATA
VDDC
VDD
VSS
Name
[2]
VDDC
VDDC
VDDC
VDDC
VDDC
PWR
IO
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
PU
PD
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PECL Clock Input.
PECL Clock Input.
External Reference or Test Clock Input.
External Reference or Test Clock Input.
Clock Outputs. See
Clock Outputs. See
Clock Outputs. See
Feedback Clock Output. Connect to FB_IN for normal operation. The
divider ratio for this output is set by FB_SEL(0:2). See
A bypass delay capacitor at this output control Input Reference or Output
Banks phase relationships.
Synchronous Pulse Output. This output is used for system
synchronization. The rising edge of the output pulse is in sync with both
the rising edges of QA (0:3) and QC(0:3) output clocks regardless of the
divider ratios selected.
Frequency Select Inputs. These inputs select the divider ratio at QA(0:3)
outputs. See
Frequency Select Inputs. These inputs select the divider ratio at QB(0:3)
outputs. See
Frequency Select Inputs. These inputs select the divider ratio at QC(0:3)
outputs. See
Feedback Select Inputs. These inputs select the divide ratio at FB_OUT
output. See
VCO Divider Select Input. When set LOW, the VCO output is divided by 2.
When set HIGH, the divider is bypassed. See
Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
PLL Enable Input. When asserted HIGH, PLL is enabled. When LOW, PLL
is bypassed.
Reference Select Input. When HIGH, the PECL inputs are selected. When
LOW, TCLK[0:1] are selected.
TCLK Select Input. When LOW, TCLK0 is selected. When HIGH TCLK1
is selected.
Master Reset or Output Enable Input. When asserted LOW, resets all of
the internal flip-flops and also disables all of the outputs. When pulled
HIGH, releases the internal flip-flops from reset and enables all of the
outputs.
Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted. When
set LOW, the inverter is bypassed.
Serial Clock Input. Clocks data at SDATA into the internal register.
Serial Data Input. Input data is clocked to the internal register to enable or
disable individual outputs. This provides flexibility in power management.
3.3V Power Supply for Output Clock Buffers.
3.3V Supply for PLL.
Common Ground.
Table 1
Table 2
Table 2
Table 2
Table 2
Table 2
Table 2
on page 1.
on page 4.
on page 4.
on page 4.
on page 4 for frequency selections.
on page 4 for frequency selections.
on page 4 for frequency selections.
Description
Table 1
on page 1.
Table 1
CY29973
Page 3 of 9
on page 1.
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