CY2077FS Cypress Semiconductor Corp, CY2077FS Datasheet - Page 7

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CY2077FS

Manufacturer Part Number
CY2077FS
Description
IC CLOCK GEN PROG 8-SOIC
Manufacturer
Cypress Semiconductor Corp
Type
Clock Generatorr
Datasheet

Specifications of CY2077FS

Pll
Yes
Input
Clock, Crystal
Output
CMOS, TTL
Number Of Circuits
1
Ratio - Input:output
1:1
Differential - Input:output
No/No
Frequency - Max
100MHz, 133MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3.3V, 5V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Frequency-max
133MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY2077FSXC
Manufacturer:
TI
Quantity:
88
Company:
Part Number:
CY2077FSXCT
Quantity:
2 500
Output Clock Switching Characteristics Industrial
Over the Operating Range
Document Number: 38-07210 Rev. *D
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
1w
1x
1y
2
3
4
5a
5b
6
7a
7b
8
9
Output duty cycle at 1.4V,
V
t
Output duty cycle at
V
t
Output duty cycle at
V
t
Output clock rise time
Output clock fall time
Startup time out of Power
down
Power down delay time
(synchronous setting)
Power down delay time
(asynchronous setting)
Power up time
Output Disable time
(synchronous setting)
Output Disable time
(asynchronous setting)
Output Enable time
(always synchronous
enable)
Peak-to-peak period
jitter
1w
1x
1y
DD
DD
DD
= t
= t
= t
/2, V
/2, V
= 4.5 – 5.5V
1A
1A
Description
1A
÷ t
÷ t
DD
DD
÷ t
1B
1B
1B
= 4.5 – 5.5V
= 3.0 – 3.6V
[4]
1 – 40 MHz, C
40 – 125 MHz, C
125 – 133 MHz, C
1 – 40 MHz, C
40 – 125 MHz, C
125 – 133 MHz, C
1– 40 MHz, C
40 – 100 MHz, C
Between 0.8 – 2.0V, V
Between 0.8 – 2.0V, V
Between 0.8 – 2.0V, V
Between 0.2V
Between 0.2V
Between 0.2V
Between 0.8V – 2.0V, V
Between 0.8 – 2.0V, V
Between 0.8 – 2.0V, V
Between 0.2V
Between 0.2V
Between 0.2V
PWR_DWN pin LOW to HIGH
PWR_DWN pin LOW to output LOW
(T= period of output clk)
PWR_DWN pin LOW to output LOW
From power on
OE pin LOW to output high-Z
(T= period of output clk)
OE pin LOW to output high-Z
OE pin LOW to HIGH
(T = period of output clk)
V
V
DD
DD
= 3.0V – 3.6V, 4.5V – 5.5V, Fo > 33 MHz, V
= 3.0V – 5.5V, Fo < 33 MHz
L
DD
DD
DD
DD
DD
DD
L
L
[5]
<= 20 pF
<= 35 pF
<= 35 pF
L
L
L
– 0.8V
– 0.8V
– 0.8V
– 0.8V
– 0.8V
– 0.8V
L
L
<= 15 pF
<= 15 pF
<= 10 pF
<= 10 pF
<= 10 pF
Test Conditions
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
= 4.5V – 5.5V, C
= 4.5V – 5.5V, C
= 4.5V – 5.5V, C
= 4.5V – 5.5V, C
= 4.5V – 5.5V, C
, V
, V
, V
, V
, V
, V
= 4.5V – 5.5V, C
DD
DD
DD
DD
DD
DD
[5]
= 4.5V – 5.5V, C
= 3.0V – 3.6V, C
= 3.0V – 3.6V, C
= 4.5V – 5.5V, C
= 3.0V – 3.6V, C
= 3.0V – 3.6V, C
L
L
L
L
L
L
= 35 pF
= 15 pF
= 10 pF
= 15 pF
= 10 pF
= 35 pF
CO
L
L
L
L
L
L
> 100 MHz
= 35 pF
= 20 pF
= 10 pF
= 35 pF
= 20 pF
= 10 pF
Min
45
45
45
45
45
45
45
40
0.3%
Typ.
T/2
T/2
10
10
80
1
1
T
T + 10
1.5T +
T+10
25ns
Max
150
1.8
1.2
0.9
3.4
4.0
2.4
1.8
1.2
0.9
3.4
4.0
2.4
1%
55
55
55
55
55
55
55
60
15
15
CY2077
2
2
Page 7 of 14
% of F
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
%
%
%
%
%
%
%
%
O
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