CY2077FS Cypress Semiconductor Corp, CY2077FS Datasheet
CY2077FS
Specifications of CY2077FS
Available stocks
Related parts for CY2077FS
CY2077FS Summary of contents
Page 1
... OE [1] XTALOUT XTALIN or external clock Note 1. When using an external clock source, leave XTALOUT floating. Cypress Semiconductor Corporation Document Number: 38-07210 Rev. *D High-accuracy EPROM Programmable Single-PLL Clock Generator Benefits ■ Enables synthesis of highly accurate and stable output clock frequencies with zero PPM ■ ...
Page 2
Pinouts Table 1. Pin Definition - 8 Pin Pin Name Pin # 5,6 PWR_DWN / OE 4 CLKOUT 8 Functional Description CY2077 is an EPROM-programmable, general-purpose, PLL-based design for ...
Page 3
Power Management Features PWR_DWN and OE options are configurable by EPROM programming for the CY2077. In PWR_DWN mode, all active circuits are powered down when the control pin is set LOW. When the control pin is set back HIGH, both ...
Page 4
Electrical Characteristics = + ° ° A Parameter Description V Low-level input voltage IL V High-level input voltage IH V Low-level output voltage OL V High-level output voltage CMOS levels V OHCMOS V High-level output ...
Page 5
Output Clock Switching Characteristics Commercial [4] Over the Operating Range Parameter Description t Output duty cycle at 1.4V 4.5 – 5.5V ÷ Output duty cycle at V /2, V ...
Page 6
Operating Conditions for Industrial Temperature Device Parameter V Supply voltage DD T Operating temperature, ambient A C Max. capacitive load on outputs for TTL levels TTL V = 4.5 – 5.5V, output frequency = 1 – 40 MHz DD V ...
Page 7
Output Clock Switching Characteristics Industrial [4] Over the Operating Range Parameter Description t Output duty cycle at 1.4V, 1 – 40 MHz 4.5 – 5.5V 40 – 125 MHz ÷ ...
Page 8
Switching Waveforms OUTPUT OUTPUT Figure 4. Power down Timing (synchronous and asynchronous modes) VDD POWER DOWN 0V CLKOUT [ 6] (synchronous ) T CLKOUT [ 7] (asynchronous ) POWER UP 0V min 30 max 30 ms ...
Page 9
Typical Rise/Fall Time [8] Trends for CY2077 Figure 7. Rise/Fall Time vs. VDD over Temperatures Rise Time vs. VDD -- CMOS duty Cycle Cload = 15pF 2.00 1.80 1.60 1.40 1.20 1.00 2.7 3.0 3.3 3.6 VDD (V) Rise Time ...
Page 10
Typical Duty Cycle [9] Trends for CY2077 Figure 9. Duty Cycle vs. V Duty Cycle vs. VDD over Temperature (TTL Duty Cycle Output, Fout=50MHz, Cload = 50pF) 55.00 53.00 51.00 49.00 47.00 45.00 4.0 4.5 5.0 5.5 VDD (V) Figure ...
Page 11
Typical Jitter Trends for CY2077 Figure 12. Period Jitter (pk-pk) vs. V 100 Figure 13. Period Jitter (pk-pk) vs. Output Frequency over Temperatures 100 Document Number: 38-07210 Rev. ...
Page 12
... Industrial (T = –40°C to 85°C) Industrial (T = –40°C to 85°C) Description Order Code none none none none none none none none none none none none CY2077FSXC CY2077FZZ CY2077FZXI CY2077FSXC CY2077 volume designs, factory programming Operating Voltage Replacement Device Description ...
Page 13
Package Diagrams Figure 14. 8-pin (150 mil Body) SOIC (Small Outline IC 0.189[4.800] 0.196[4.978] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] Figure 15. 8-pin (4.40-mm Body) TSSOP (Thin Shrunk Small Outline Package) 1 4.30[0.169] 4.50[0.177] 8 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] ...
Page 14
... Updated package diagrams 01/06/09 Updated template. CY2077FS removed from the active part number table. Added CY2077FZXI and CY2077FZXIT to the Ordering Information table. Corrected wording about when the weak output pull-down is active. Added to Table 1 to indicate that PWR_DWN is active low and OE is active high ...