LMX2541SQE3030E/NOPB National Semiconductor, LMX2541SQE3030E/NOPB Datasheet - Page 46

• Manufacturer Part Number: LMX2541SQE3030E/NOPB
• Description: IC PLL FREQ SYNTH W/VCO 36LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of LMX2541SQE3030E/NOPB

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 3.23GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-LLP
• Frequency-max: 3.23GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMX2541SQE3030ETR

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ORDER[2:0] -- Delta Sigma Modulator Order
This word determines the order of the delta sigma modulator in the PLL. In general, higher order fractional modulators tend to
reduce the primary fractional spurs that occur at increments of the channel spacing, but can also create spurs that are at a fraction
of the channel spacing. The optimal choice of modulator order is very application specific, however, a third order modulator is a
good starting point. The first order modulator has no analog compensation or dithering
DITH[1:0] -- Dithering
Dithering randomizes the delta sigma modulator output. This reduces sub-fractional spurs at the expense of adding phase noise.
In general, it is recommended to keep the dithering strength at None or Weak for most applications. Dithering should never be
used when the device is used in integer mode or a first order modulator. When using dithering with the other delta sigma modulator
orders, it is beneficial to disable it in the case where the fractional numerator is zero, since it can actually create sub-fractional
spurs.
CPT - Charge Pump TRI-STATE
When this bit is enabled, the charge pump is at TRI-STATE. The TRI-STATE mode could be useful for open loop modulation
applications or as diagnostic tool for measuring the VCO noise, but is generally not used.
DLOCK[2:0] - Controls for Digital Lock detect
This word controls operation of the digital lock detect function through selection of the window sizes (ε and δ). In order to indicate
the PLL is locked, there must be 5 consecutive phase detector output cycles in which the time offset between the R and N counter
outputs is less than ε. This will cause the Ftest/LD pin output to go high. Once lock is indicated, it will remain in this state until the
time offset between the R and N counter outputs exceeds δ. For this device, ε and δ are the same. If the OSCin signal goes away,
the digital lock detect circuit will reliably indicate an unlocked condition. Consult the functional description for more details. A larger
window size makes the lock detect circuit less sensitive, but may be necessary in some situations to reduce chattering.
ORDER
5-7
0
1
2
3
4
(Default)
DLOCK
6 -7
Second Order
0
1
2
3
4
5
Delta Sigma
Fourth Order
Illegal States
Third Order
Modulator
First Order
Disabled
DITH
0
1
2
3
CPT
0
1
Fractional
Integer
Mode
n/a
46
Dithering Strength
Normal Operation
Charge Pump
TRI-STATE
Disabled
Medium
Strong
Weak
This has no analog compensation or dithering
Traditional Delta Sigma Operation
Window Size
Allows larger N Counter
Reserved
(ε and δ)
11.5
13.5
3.5
5.5
7.5
9.5
Comments
n/a