LMX2541SQE2060E/NOPB National Semiconductor, LMX2541SQE2060E/NOPB Datasheet - Page 55

• Manufacturer Part Number: LMX2541SQE2060E/NOPB
• Description: IC PLL FREQ SYNTH W/VCO 36LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of LMX2541SQE2060E/NOPB

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 2.24GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-LLP
• Frequency-max: 2.24GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMX2541SQE2060ETR

CHANGE in Current Consumption in
Bypass Mode as a Function of
VCOGAIN and OUTTERM
CHANGE in Current Consumption in
Divided Mode as a Function of
DIVGAIN and OUTTERM
3.8 LOOP FILTER
Loop filter design can be rather complicated, but there are
design tools and references available at www.national.com.
The loop bandwidth can impact the size of loop filter capaci-
tors and also how the phase noise is filtered. For optimal
integrated phase noise, choose the bandwidth to be about
20% wider than the frequency where the in-band PLL phase
noise (as described in
VCO noise cross. This optimal loop bandwidth may need ad-
justment depending on the application requirements. Reduc-
tion of spurs can be achieved by reducing the loop bandwidth.
On the other hand, a wider loop bandwidth may be required
for faster lock time. Note that using the integrated loop filter
components can lead to a significant restriction on the loop
bandwidth and should be used with care. 2 kΩ for R3_LF and
R4_LF is a good starting point. If the integrated loop filter re-
stricts the loop bandwidth, then first try to relieve this restric-
tion by reducing the integrated loop filter resistors and then
reduce the capacitors only if necessary.
3.9 CONFIGURING THE LMX2541 FOR OPTIMAL
PERFORMANCE
1.
2.
Determine the Channel Spacing (f
For a system that has a VCO that tunes over several
frequencies, the channel spacing is the tuning increment.
In the case that the VCO frequency is fixed, this channel
spacing is the greatest number that divides both the VCO
frequency and the OSCin frequency.
Determine OSCin Frequency (f
If the OSCin frequency is not already determined, then
there are several considerations. A higher frequency is
generally, but not always, preferable. One reason for this
is that it has a higher slew rate if it is a sine wave. Another
reason is that the clock for the VCO frequency calibration
is based on the OSCin frequency and in general will run
faster for higher OSCin frequencies.
Although a higher OSCin frequency is desirable, there
are also reasons to use a lower frequency. If the OSCin
frequency is strategically chosen, the worst case
12
15
12
15
3
6
9
3
6
9
-26.0
-18.5
-11.1
-24.4
-16.2
+3.3
+7.1
-3.8
-8.3
-0.5
3
3
3.4 PLL PHASE
-22.3
-15.5
-21.7
-14.6
+3.7
+6.0
-9.0
-2.6
-7.6
-0.7
6
6
VCOGAIN
DIVGAIN
-18.6
-12.6
-18.7
-12.6
+4.0
+5.2
-6.9
-1.4
-6.8
-0.7
OSCin
9
9
NOISE) and open loop
CH
)
)
-15.1
-15.9
-10.1
+0.0
+4.5
+0.0
+4.9
-9.7
-4.7
-5.0
12
12
-11.8
-13.3
+1.5
+5.3
+1.3
+5.6
-6.9
-2.5
-8.0
-3.2
15
15
55
3.
4.
5.
6.
3.9 EXTERNAL VCO MODE
The LMX2541 also has provisions to be driven with an exter-
nal VCO as well. In this mode, the user has the option of using
the RFout pin output, although if this pin is used, the VCO
input frequency is restricted to 4 GHz. If not used, the RFout
pin should be left open. The VCO input is connected to the
ExtVCOin pin. Because the internal VCO is not being used,
the part option that is being used does not have a large impact
on phase noise or spur performance. It is also possible to
switch between both Full Chip mode and External VCO mode.
3.10 INTERNAL VCO DIGITAL CALIBRATION TIME
When the LMX2541 is used in full chip mode, the integrated
VCO can impact the lock time of the system. This digital cal-
ibration chooses the closest VCO frequency band, which
typically gets the device within a frequency error 10 MHz or
less of the final settling frequency, although this final frequen-
cy error can change slightly between the different options of
the LMX2541. Once this digital calibration is finished, this re-
maining frequency error must settle out, and this remaining
lock time is dictated by the loop bandwidth.
Based on measured data, this digital calibration time can be
approximated by the following formula:
Locktime
Symbo1
fractional spur channels might fall out of band. Also, if the
OSCin frequency can be chosen such that the fractional
denominator can avoid factors of 2 and/or 3, the sub-
fractional spurs can be reduced.
Determine the Phase Detector Frequency (f
Charge Pump Gain (K
(FDEN)
In general, choose the highest phase detector frequency
and charge pump gain, unless it leads to loop filter
capacitor values that are unrealistically large for a given
loop bandwidth. In this case, reducing either the phase
detector frequency or the charge pump gain can yield
more feasible capacitor values. Other reasons for not
using the highest charge pump gain is to allow some
adjustment margin to compensate for changes in the
VCO gain or allow the use of Fastlock.
For choosing the fractional denominator, start with FDEN
= f
reasons to choose larger equivalent fractions.
Design the Loop Filter
Determine the Modulator Order
Determine Dithering and Potential Larger Equivalent
Fractional Value
CLK
LockTime = A + B/CLK + C·ΔF + D·( ΔF/CLK )
PD
ΔF
A
B
C
D
/f
CH
. As discussed previously, there might be
OSC_FREQ
f
OSC_FREQ
f
OSCin
f
OSCin
OSCin
OSC_FREQ
PD
Varies
Varies
/ 8 for 128
Value
3800
/ 4 for 64
) and Fractional Denominator
/ 2 for 0
0.1
30
2
≤
≤
127
≤
63
≤
≤
www.national.com
Units
None
None
MHz
PD
µs
μs
μs
µs
) ,