EL4585CSZ Intersil, EL4585CSZ Datasheet - Page 4

• Manufacturer Part Number: EL4585CSZ
• Description: IC PLL VIDEO GP 36MHZ 16-SOIC
• Manufacturer: Intersil
• Type: Phase Lock Loop (PLL)r

Specifications of EL4585CSZ

• Pll: Yes
• Input: Clock
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: No/No
• Frequency - Max: 36MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 36MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
Pin NUMBER
1, 2, 16
10
12
13
14
15
11
PROG A (PIN 16)
3
4
5
6
7
8
9
0
0
0
0
1
1
1
1
CHARGE PUMP
OSC/VCO OUT
PROG B, C, A
OSC/VCO IN
DIV SELECT
PIN NAME
LOCK DET
HSYNC IN
CLK OUT
EXT DIV
VDD (A)
VDD (D)
VSS (A)
VSS (D)
COAST
OUT
4
Digital inputs to select ÷ N value for internal counter. See Table 1 for values.
Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit.
Analog positive supply for oscillator, PLL circuits.
Input from external VCO.
Analog ground for oscillator, PLL circuits.
Connect to loop filter. If the H
into the filter capacitor to increase VCO frequency. If H
current is pumped out of the filter capacitor to decrease VCO frequency. During coast mode or when
locked, charge pump goes to a high impedance state.
Divide select input. When high, the internal divider is enabled and EXT DIV becomes a test pin, outputting
CLK ÷ 2N. When low, the internal divider is disabled and EXT DIV is an input from an external ÷N.
Three-state logic input. Low (< 1/3*V
High (> 2/3*V
Horizontal sync pulse (CMOS level) input.
Positive supply for digital, I/O circuits.
Lock detect output. Low level when PLL is locked. Pulses high when out of lock.
External divide input when DIV SEL is low, internal ÷ 2N output when DIV SEL is high.
Ground for digital, I/O circuits.
Buffered output of the VCO.
PROG B (PIN 1)
0
0
1
1
0
0
1
1
CC
) = coast mode.
TABLE 1. VCO DIVISORS
EL4585
SYNC
phase is leading or H
CC
) = normal mode, Hi Z (or 1/3 to 2/3*V
PROG C (PIN 2)
FUNCTION
0
1
0
1
0
1
0
1
SYNC
SYNC
phase is lagging or frequency < CLK ÷ 2N,
frequency > CLK ÷ 2N, current is pumped
CC
DIV VALUE (N)
) = fast lock mode,
1702
1728
1888
2270
1364
1716
1560
1820
September 3, 2009
FN7175.4