MK1714-02R IDT, Integrated Device Technology Inc, MK1714-02R Datasheet - Page 4

• Manufacturer Part Number: MK1714-02R
• Description: IC CLK MULT SPRD SPECTRUM 20QSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Multiplierr

Specifications of MK1714-02R

• Pll: Yes with Bypass
• Input: Clock, Crystal
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-QSOP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 800-2003-5; MK1714-02R

External Components
The MK1714-02 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50 trace (a commonly used trace
impedance) place a 33 resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20 .
Crystal Tuning Load Capacitors
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal
(C
pF. Example: For a crystal with a 16 pF load capacitance,
each crystal capacitor would be
[16 - 6]*2 = 20 pF.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
IDT™ SPREAD SPECTRUM MULTIPLIER CLOCK
MK1714-02
SPREAD SPECTRUM MULTIPLIER CLOCK
L
-6)*2. In this equation, C
L
= crystal load capacitance in
4
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI the 33 series termination resistor, if
needed, should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the MK1714-02. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
Powerup Considerations
To insure proper operation of the spread spectrum
generation circuit, some precautions must be taken in the
implementation of the MK1714-02.
1) An input signal should not be applied to ICLK until VDD
is stable (within 10% of its final value). This requirement can
be easily met by operating the MK1714-02 and the ICLK
source from the same power supply.
2) LEE should not be enabled (taken high) until after the
power supplies and input clock are stable. This requirement
can be met by direct control of LEE by system logic; for
example, a “power good” signal. Another solution is to leave
LEE unconnected to anything but a 0.01 F capacitor to
ground. The pull-up resistor on LEE will charge the
capacitor and provide approximately a 700 s delay until
spread spectrum is enabled.
3) If the input frequency is changed during operation,
disable spread spectrum until the input clock stabilizes at
the new frequency.
MK1714-02
REV K 051310
SSCG